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| Content Provider | IEEE Xplore Digital Library |
|---|---|
| Author | Ben-Asher, Y. Citron, D. Haber, G. |
| Copyright Year | 2004 |
| Description | Author affiliation: Dept. of Comput. Sci., Haifa Univ., Israel (Ben-Asher, Y.) |
| Abstract | Summary form only given. We consider the problem of compiling programs, written in a general high-level programming language, into hardware circuits executed by an FPGA (field programmable gate array) unit. In particular, we consider the problem of synthesizing nested loops that frequently access array elements stored in an external memory (outside the FPGA). We propose an aggressive compilation scheme, based on loop unrolling and code flattening techniques, where array references from/to the external memory are overlapped with uninterrupted hardware evaluation of the synthesized loop's circuit. We implement a restricted programming language called DOL based on the proposed compilation scheme and our experimental results provide preliminary evidence that aggressive compilation can be used to compile large code segments into circuits, including overlapping of hardware operations and memory references. |
| Sponsorship | IEEE Comput. Soc. Tech. Committee on Parallel Processing |
| File Size | 1499416 |
| File Format | |
| ISBN | 0769521320 |
| DOI | 10.1109/IPDPS.2004.1303133 |
| Language | English |
| Publisher | Institute of Electrical and Electronics Engineers, Inc. (IEEE) |
| Publisher Date | 2004-04-26 |
| Publisher Place | USA |
| Access Restriction | Subscribed |
| Rights Holder | Institute of Electrical and Electronics Engineers, Inc. (IEEE) |
| Subject Keyword | Hardware Field programmable gate arrays Computer languages Circuit synthesis Acceleration Power generation economics Registers Decoding Parallel processing Application specific integrated circuits |
| Content Type | Text |
| Resource Type | Article |
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