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| Content Provider | IEEE Xplore Digital Library |
|---|---|
| Author | Sezer, S. Toal, C. Garcia, E. Stewart, V. |
| Copyright Year | 2004 |
| Abstract | Summary form only given. We present the hardware architecture and implementation of a reconfigurable tag computation circuit for terabit packet scheduling for future QoS aware core routers. The presented implementation provides a platform for a runtime configurable scheduling architecture that is able to reallocate bandwidth on the fly. The system is implemented using FPGA technology and provides extended programmability to adapt the tag computation to a range of custom packet scheduling policies. The hardware architecture is parallel and pipelined enabling an aggregated throughput rate of 175 million tag computations per second, easily out performing current QoS router solutions. The high-level system breakdown is described and synthesis results for Altera FPGA technology are presented. |
| Sponsorship | IEEE Comput. Soc. Tech. Committee on Parallel Processing |
| File Size | 1425534 |
| File Format | |
| ISBN | 0769521320 |
| DOI | 10.1109/IPDPS.2004.1303103 |
| Language | English |
| Publisher | Institute of Electrical and Electronics Engineers, Inc. (IEEE) |
| Publisher Date | 2004-04-26 |
| Publisher Place | USA |
| Access Restriction | Subscribed |
| Rights Holder | Institute of Electrical and Electronics Engineers, Inc. (IEEE) |
| Subject Keyword | Computer architecture Scheduling algorithm Hardware Field programmable gate arrays Circuits Runtime Processor scheduling Bandwidth Throughput Concurrent computing |
| Content Type | Text |
| Resource Type | Article |
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