NDLI: SPEAR: a hybrid model for speculative pre-execution

Content Provider	IEEE Xplore Digital Library
Author	Ro, W.W. Gaudiot, J.-L.
Copyright Year	2004
Description	Author affiliation: Dept. of Electr. Eng., Univ. of Southern California, CA, USA (Ro, W.W.)
Abstract	Summary form only given. Speculative preexecution achieves efficient data prefetching by running additional prefetching threads on spare hardware contexts. Various implementations for speculative preexecution have been proposed, including compiler-based static approaches and hardware-based dynamic approaches. A static approach defines the p-thread at compile time and executes it as a stand-alone running thread. Therefore, it cannot efficiently take the dynamic events into account and requires a higher fetch bandwidth. Conversely, a hardware approach is, by essence, able to dynamically use the runtime information. However, it requires more complex hardware and also lacks global program information on data and control flow. We propose SPEAR (Speculative Preexecution Assisted by CompileR), a preexecution model which is a hybrid of the two approaches. It relies on a post-compiler to extract the p-thread code from program binaries and uses specially designed hardware to trigger the execution of the p-thread. For this purpose, an automated software tool for p-thread identification has been developed and a modified SMT model with the specially designed front-end is proposed.
Sponsorship	IEEE Comput. Soc. Tech. Committee on Parallel Processing
File Size	1471038
File Format	PDF
ISBN	0769521320
DOI	10.1109/IPDPS.2004.1303008
Language	English
Publisher	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Publisher Date	2004-04-26
Publisher Place	USA
Access Restriction	Subscribed
Rights Holder	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Subject Keyword	Prefetching Yarn Hardware Delay Bandwidth Runtime Data mining Software tools Surface-mount technology Microprocessors
Content Type	Text
Resource Type	Article

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2	Indian Institute of Technology Kharagpur	Host Institute of the Project: The host institute of the project is responsible for providing infrastructure support and hosting the project	https://www.iitkgp.ac.in
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4	Project PI / Joint PI	Principal Investigator and Joint Principal Investigators of the project	Dr. B. Sutradhar bsutra@ndl.gov.in Prof. Saswat Chakrabarti will be added soon
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