NDLI: Self-checking test circuits for latches and flip-flops

Content Provider	IEEE Xplore Digital Library
Author	Ribas, R.P. Yuyang Sun Reis, A.I. Ivanov, A.
Copyright Year	2011
Description	Author affiliation: Federal University of Rio Grande do Sul, Av. Bento Gonçalves, 9500, Porto Alegre, RS, 91501-970, Brazil (Reis, A.I.) \|\| University of British Columbia, 2356 Main Mall, Vancouver, BC, V6T 1Z4, Canada (Ribas, R.P.; Yuyang Sun; Ivanov, A.)
Abstract	This work proposes design strategies applicable to self-test circuits for the functional validation of latches and flip-flops. The proposed methodology is also useful for, delay test and power consumption analysis that can also be performed over the circuits under test. Moreover, the evaluation of the impacts on circuit operation due to power supply variations and nanometer aging effects can be explored through the self-timed execution mode by monitoring the run frequency. The self-timed and self-checking characteristics make the proposed solutions very attractive for testing standard cell libraries as well as for comparing different implementations of such storage elements. We have validated the addressed strategies at transistor level through electrical simulations.
Starting Page	210
Ending Page	213
File Size	235060
Page Count	4
File Format	PDF
ISBN	9781457710537
e-ISBN	9781457710568
DOI	10.1109/IOLTS.2011.5993846
Language	English
Publisher	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Publisher Date	2011-07-13
Publisher Place	Greece
Access Restriction	Subscribed
Rights Holder	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Subject Keyword	Flip-flops Latches Radiation detectors Libraries Silicon Clocks Steady-state cell library test circuit digital design flip-flop latch
Content Type	Text
Resource Type	Article

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4	Project PI / Joint PI	Principal Investigator and Joint Principal Investigators of the project	Dr. B. Sutradhar bsutra@ndl.gov.in Prof. Saswat Chakrabarti will be added soon
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