NDLI: DAQ system with RACEway switch for PHOBOS experiment at RHIC

Content Provider	IEEE Xplore Digital Library
Author	Kulinich, P. Sarin, P. Sukhanov, A.
Copyright Year	2002
Description	Author affiliation: Lab. for Nucl. Sci., MIT, Cambridge, MA, USA (Kulinich, P.; Sarin, P.)
Abstract	The PHOBOS data acquisition system based on a RACEway switching network is described. Occupying a single VME crate, the system utilizes 24 PPC-750 CPUs working in parallel to compress data from 135,168 silicon pad detectors, and an UltraSPARC VME host for event building and data storage. Lossless Huffman coding is used for compression; this reduces the event size three times. The two-host disk array is used to stage data before sending them over a Gigabit Ethernet to the RHIC Central Computing Facility. The writing and reading are done simultaneously at 40 MB/sec. All trigger and control logic is formed using universal programmable logic VME modules, which can be programmed in situ, even when the system is running. The data is written in the popular ROOT format; all data processing and run control software is written using the ROOT framework. The slow control and configuration makes use of an Oracle database to store configuration and monitor parameters. The system has been taking data from the Phobos experiment at RHIC since June 2000. The system is capable to take data with the rate of 200 events/sec or 30 MB/sec.
Starting Page	81
Ending Page	84
File Size	315007
Page Count	4
File Format	PDF
ISBN	0780373243
ISSN	10823654
DOI	10.1109/NSSMIC.2001.1008414
Language	English
Publisher	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Publisher Date	2001-11-04
Publisher Place	USA
Access Restriction	Subscribed
Rights Holder	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Subject Keyword	Switches Data acquisition Programmable logic arrays Programmable logic devices Programmable control Silicon Event detection Detectors Memory Huffman coding
Content Type	Text
Resource Type	Article

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1	Ministry of Education (GoI), Department of Higher Education	Sanctioning Authority	https://www.education.gov.in/ict-initiatives
2	Indian Institute of Technology Kharagpur	Host Institute of the Project: The host institute of the project is responsible for providing infrastructure support and hosting the project	https://www.iitkgp.ac.in
3	National Digital Library of India Office, Indian Institute of Technology Kharagpur	The administrative and infrastructural headquarters of the project	Dr. B. Sutradhar bsutra@ndl.gov.in
4	Project PI / Joint PI	Principal Investigator and Joint Principal Investigators of the project	Dr. B. Sutradhar bsutra@ndl.gov.in Prof. Saswat Chakrabarti will be added soon
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