NDLI: FPGA based front-end electronics for a high resolution PET scanner

Content Provider	IEEE Xplore Digital Library
Author	Young, J.W. Moyers, J.C. Lenox, M.
Copyright Year	2000
Description	Author affiliation: CTI PET Syst. Inc., Knoxville, TX, USA (Young, J.W.)
Abstract	A high resolution PET scanner requiring processing electronics for 936 block technology channels and just under sixty-thousand crystal elements has been developed. With the advances in flexibility, number of gates, lower costs and speed of FPGAs, an FPGA implementation of the front-end processing electronics was chosen over the traditional discrete logic or ASIC. The FPGA architecture reduced the development time and risks compared to a mask-based ASIC architecture while keeping costs and electronics packing density comparable. The extensive use FPGAs enables much faster circuit realization and a very efficient logic utilization by allowing reconfiguration of the electronics functionality to support system setup, self-diagnostics, and several calibration modes for detector setup. Logic realized within the FPGAs performs the crystal selection, energy qualification, time correction, depth of interaction determination, and event counting functions. Since the FPGAs are in-circuit reconfigurable, the functionality of the electronics is easily modified to support the different modes of operation. Thus the development time is reduced as well as the amount of electronics required, saving board area, power consumption and costs.
Starting Page	902
Ending Page	906
File Size	551305
Page Count	5
File Format	PDF
ISBN	0780356969
ISSN	10823654
DOI	10.1109/NSSMIC.1999.845809
Language	English
Publisher	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Publisher Date	1999-10-24
Publisher Place	USA
Access Restriction	Subscribed
Rights Holder	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Subject Keyword	Field programmable gate arrays Positron emission tomography Costs Reconfigurable logic Application specific integrated circuits Logic circuits Calibration Detectors Qualifications Energy consumption
Content Type	Text
Resource Type	Article

Sl.	Authority	Responsibilities	Communication Details
1	Ministry of Education (GoI), Department of Higher Education	Sanctioning Authority	https://www.education.gov.in/ict-initiatives
2	Indian Institute of Technology Kharagpur	Host Institute of the Project: The host institute of the project is responsible for providing infrastructure support and hosting the project	https://www.iitkgp.ac.in
3	National Digital Library of India Office, Indian Institute of Technology Kharagpur	The administrative and infrastructural headquarters of the project	Dr. B. Sutradhar bsutra@ndl.gov.in
4	Project PI / Joint PI	Principal Investigator and Joint Principal Investigators of the project	Dr. B. Sutradhar bsutra@ndl.gov.in Prof. Saswat Chakrabarti will be added soon
5	Website/Portal (Helpdesk)	Queries regarding NDLI and its services	support@ndl.gov.in
6	Contents and Copyright Issues	Queries related to content curation and copyright issues	content@ndl.gov.in
7	National Digital Library of India Club (NDLI Club)	Queries related to NDLI Club formation, support, user awareness program, seminar/symposium, collaboration, social media, promotion, and outreach	clubsupport@ndl.gov.in
8	Digital Preservation Centre (DPC)	Assistance with digitizing and archiving copyright-free printed books	dpc@ndl.gov.in
9	IDR Setup or Support	Queries related to establishment and support of Institutional Digital Repository (IDR) and IDR workshops	idr@ndl.gov.in

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