NDLI: A new technique for the fabrication of thin silicon radiation detectors

Content Provider	IEEE Xplore Digital Library
Author	Foulon, F. Rousseau, L. Babadjian, L. Spirkovitch, S. Brambilla, A. Bergonzo, P.
Copyright Year	1999
Description	Author affiliation: CEA, Centre d'Etudes Nucleaires de Saclay, Gif-sur-Yvette, France (Foulon, F.)
Abstract	The fabrication of silicon radiation detectors with thicknesses lower than 30 /spl mu/m requires non-standard processing equipment and procedures. Such detectors are commonly manufactured by vias in thick silicon wafers of typically 300 /spl mu/m in order to locally create on small areas thin detectors. Since the etching step controls the thickness and uniformity of the detector, it must provide a constant and controllable etch rate and should not modify the surface microroughness, rendering this manufacturing technique critical. As an alternative, we have developed a new technique for the fabrication of thin detectors based on the use of substrates presenting a buried etch-stop layer. The detector thickness, its uniformity and the surface roughness are fixed and controlled by the substrate specifications. 5 to 30 /spl mu/m thick pin silicon diodes with surfaces ranging from 1 to 100 mm/sup 2/ have been fabricated. Using this technique, thickness uniformity as low as /spl plusmn/0.05 /spl mu/m can be obtained on 5 /spl mu/m thick detectors over 100 mm/sup 2/ area. 30 /spl mu/m thick pin detectors (S=64 mm/sup 2/) are fully depleted at zero bias and exhibit an energy resolution of less than 120 keV (/spl sim/2 %) for 5.5 MeV alpha particles. This constitutes a breakthrough towards the low cost fabrication of thin silicon radiation detectors using planar technology.
Starting Page	681
Ending Page	683
File Size	272768
Page Count	3
File Format	PDF
ISBN	0780350219
ISSN	10823654
DOI	10.1109/NSSMIC.1998.775229
Language	English
Publisher	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Publisher Date	1998-11-08
Publisher Place	Canada
Access Restriction	Subscribed
Rights Holder	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Subject Keyword	Fabrication Etching Thickness control Rough surfaces Surface roughness Silicon radiation detectors Manufacturing Diodes Energy resolution Alpha particles
Content Type	Text
Resource Type	Article

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1	Ministry of Education (GoI), Department of Higher Education	Sanctioning Authority	https://www.education.gov.in/ict-initiatives
2	Indian Institute of Technology Kharagpur	Host Institute of the Project: The host institute of the project is responsible for providing infrastructure support and hosting the project	https://www.iitkgp.ac.in
3	National Digital Library of India Office, Indian Institute of Technology Kharagpur	The administrative and infrastructural headquarters of the project	Dr. B. Sutradhar bsutra@ndl.gov.in
4	Project PI / Joint PI	Principal Investigator and Joint Principal Investigators of the project	Dr. B. Sutradhar bsutra@ndl.gov.in Prof. Saswat Chakrabarti will be added soon
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