NDLI: A front end electronic design with sliding ADC channels and X-Y decoder for a position sensitive scintillator block array

Content Provider	IEEE Xplore Digital Library
Author	Wai-Hoi Wong Guoji Hu Weizhao Lu Hicks, K. Uribe, J.
Copyright Year	1996
Description	Author affiliation: M.D. Anderson Cancer Center, Texas Univ., Houston, TX, USA (Wai-Hoi Wong; Guoji Hu; Weizhao Lu; Hicks, K.; Uribe, J.)
Abstract	This is an electronic design for a position sensitive detector system with a large array of crystal blocks (each block is composed of many crystals). The design goals are parts and space reduction. Each PMT has its fast amplifier and triggered integrator. Nine flash ADC, 3 adders, 2 EPROM and 10 program logic devices are used to determine the scintillation location for an array of 27 PMT and 784 crystals. The fast signals from one or more PMT clusters are summed. The fast summed signals are thresholded and sent to a GAL to determines the probable scintillation zone (several blocks) and to turn on the associated PMT integrators. After integration, the GAL also drives a set of ultra-fast analog switches to connect the flash ADC set (9 units) to the PMT integration channels in the scintillation zone. The 9 ADC output (integrated pulses with good photon statistics) are latched and compared. The comparator result determines which block in the probable zone is firing and the appropriate 4 ADC are selected and bused into a position decoder composed of 3 adders and a EPROM. The EPROM outputs the X-Y position along with the block-address. The circuit is pipelined and driven by a 250 MHz master clock. The maximum event-processing rate for the circuit and a random radiation source is 2/spl times/10/sup 6//sec (with 10:1 randomness allowance).
Starting Page	1031
Ending Page	1035
File Size	429900
Page Count	5
File Format	PDF
ISBN	078033180X
DOI	10.1109/NSSMIC.1995.510441
Language	English
Publisher	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Publisher Date	1995-10-21
Publisher Place	USA
Access Restriction	Subscribed
Rights Holder	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Subject Keyword	EPROM Crystals Adders Programmable logic arrays Circuits Position sensitive particle detectors Solid scintillation detectors Sensor arrays Logic devices Switches
Content Type	Text
Resource Type	Article

Sl.	Authority	Responsibilities	Communication Details
1	Ministry of Education (GoI), Department of Higher Education	Sanctioning Authority	https://www.education.gov.in/ict-initiatives
2	Indian Institute of Technology Kharagpur	Host Institute of the Project: The host institute of the project is responsible for providing infrastructure support and hosting the project	https://www.iitkgp.ac.in
3	National Digital Library of India Office, Indian Institute of Technology Kharagpur	The administrative and infrastructural headquarters of the project	Dr. B. Sutradhar bsutra@ndl.gov.in
4	Project PI / Joint PI	Principal Investigator and Joint Principal Investigators of the project	Dr. B. Sutradhar bsutra@ndl.gov.in Prof. Saswat Chakrabarti will be added soon
5	Website/Portal (Helpdesk)	Queries regarding NDLI and its services	support@ndl.gov.in
6	Contents and Copyright Issues	Queries related to content curation and copyright issues	content@ndl.gov.in
7	National Digital Library of India Club (NDLI Club)	Queries related to NDLI Club formation, support, user awareness program, seminar/symposium, collaboration, social media, promotion, and outreach	clubsupport@ndl.gov.in
8	Digital Preservation Centre (DPC)	Assistance with digitizing and archiving copyright-free printed books	dpc@ndl.gov.in
9	IDR Setup or Support	Queries related to establishment and support of Institutional Digital Repository (IDR) and IDR workshops	idr@ndl.gov.in

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