NDLI: Hybrid ferromagnet-semiconductor gates for nonvolatile memory

Content Provider	IEEE Xplore Digital Library
Author	Johnson, M. Bennett, B.R. Yang, M.J. Miller, M.M. Shanabrook, B.V.
Copyright Year	1998
Description	Author affiliation: Naval Res. Lab., Washington, DC, USA (Johnson, M.)
Abstract	A novel magnetoelectronic device for nonvolatile memory applications is presented, and characteristics of a nonvolatile random access memory (NRAM) cell are discussed. In contrast with a magnetoresistive approach, this device uses a single bistable ferromagnetic layer which is electrically isolated from a microstructured semiconducting Hall cross. A micron scale prototype has demonstrated binary output states of 0 and 100 mV (0 and 20 /spl Omega/) at room temperature. A submicron cell, with a 0.5 /spl mu/m by 2.8 /spl mu/m Permalloy element, has been fabricated and demonstrated excellent properties. Initial sets of prototypes have been fabricated on high mobility III-V semiconductor heterostructures, but the device concept can be used with Si. This novel approach has several advantages. The basic device is a simple bilayer, requiring only two lithographic levels and a single alignment. It is compatible with GaAs or CMOS processing, and device isolation can be readily achieved using Schottky diodes. The simplicity of the device places minimal requirements on fabrication of the ferromagnetic element, and evidence from prototypes suggests high yield. Signal levels are high, and the device shows inverse scalability: smaller devices have improved output characteristics.
Starting Page	78
Ending Page	83
File Size	669377
Page Count	6
File Format	PDF
ISBN	0780345185
DOI	10.1109/NVMT.1998.723225
Language	English
Publisher	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Publisher Date	1998-06-24
Publisher Place	USA
Access Restriction	Subscribed
Rights Holder	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Subject Keyword	Nonvolatile memory Prototypes Magnetoelectronics Random access memory Magnetoresistance Semiconductivity Temperature III-V semiconductor materials Gallium arsenide CMOS process
Content Type	Text
Resource Type	Article

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4	Project PI / Joint PI	Principal Investigator and Joint Principal Investigators of the project	Dr. B. Sutradhar bsutra@ndl.gov.in Prof. Saswat Chakrabarti will be added soon
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