NDLI: Static FRAM: an emerging nonvolatile memory technology

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Seventh Biennial IEEE International Nonvolatile Memory Technology Conference. Proceedings (Cat. No.98EX141)

Seventh Biennial IEEE International Nonvolatile Memory Technology Conference. Proceedings (Cat. No.98EX141)

Research and education opportunities in memory technology at the National Science Foundation

Air Force space system requirements for non-volatile memory-a lab perspective

Tunnel oxide and ETOX/sup TM/ flash scaling limitation

Magnetic recording technology-advances through the year 2000 and beyond

Current issues in rewritable optical disk data storage

Overview of non-volatile memory packaging needs and approaches for space based systems

2k nonvolatile shadow RAM and 256k EEPROM SONOS nonvolatile memory development

A 32k/spl times/8 radiation-hardened CMOS/SONOS EEPROM

A 42.5 mm/sup 2/ 1 Mb nonvolatile ferroelectric memory utilizing advanced architecture for enhanced reliability

Static FRAM: an emerging nonvolatile memory technology

Microcontrollers with ferroelectric embedded memory

A 32-bit RISC microcontroller with 448K bytes of embedded flash memory

Optimizing GMR spin valves: the outlook for improved properties

A practical 256K GMR NV memory for high shock applications

High density pseudo spin valve magnetoresistive RAM

Magneto-resistive IC memory limitations and architecture implications

Micro Drive-a pluggable one-inch disk drive for portable devices

Magnetic tape recording technology and devices

High density data storage based on the atomic force microscope

Nonvolatile optical storage in photorefractive crystals

Advances in 3D two-photon optical storage devices

Recent developments in vertical Bloch line data storage

Spatial and electronic manipulation of silicon nanocrystals by atomic force microscopy

Hybrid ferromagnet-semiconductor gates for nonvolatile memory

Bacteriorhodopsin-based volumetric optical memory

Nonvolatile memory based on mobile protons

High density packaging of flash memory

Micro-ball grid arrays: a practical chip-size packaging solution for nonvolatile memory applications

Low-cost, high density non volatile memory for military and space applications

Reliability of reprogrammable nonvolatile memories

Protecting COTS ICs for space

Rapid development of MCM-based nonvolatile memory subsystems

Investigation of tunneling current through thin dielectrics

Proceedings of Nonvolatile Memory Technology Conference

[1993 Proceedings] Fifth Biennial Nonvolatile Memory Technology Review

Static FRAM: an emerging nonvolatile memory technology

Content Provider	IEEE Xplore Digital Library
Author	Evans Jr., J.T. Suizu, R.I.
Copyright Year	1998
Description	Author affiliation: Radiant Technol. Inc., Albuquerque, NM, USA (Evans, J.T., Jr.)
Abstract	Summary form only given. Nondestructively read ferroelectric memories can be achieved using the ferroelectric material as the FET gate oxide. CMOS FETs with ferroelectric gate oxides are very difficult to build but ferroelectric gate TFTs have a robust process that differs from that of the ferroelectric capacitor by only one mask layer. The static FRAM (SFRAM) is one such device. It consists of a Pt-PZT capacitor where the top Pt electrode is replaced by a semiconducting oxide. The ferroelectric material polarization state modulates the semiconducting electrode conductivity. The magnitude of the conductivity change can be process controlled to range from 3:1 to 300:1 depending on the product requirements. Current sensing amplifiers can detect the transistor state in as little as 15 ns. Combining one CMOS transistor as the pass gate with each SFRAM transistor, large nonvolatile memory arrays can be built with 40 /spl mu/m/sup 2/ cell sizes, <100 ns cycle times, and using simple SRAM asynchronous three line control. Write operations for SFRAM memory cells are identical to those of the FRAM and have similar power consumption. However, SFRAM source and drain contacts are ohmic, allowing read operations using voltages as low as 50 mV and consuming infinitesimal memory array power. The devices exhibit little fatigue or imprint and can operate with V/sub cc/ as low as 3.5 V. Retention, the most difficult factor to control in ferroelectric transistors, has been demonstrated at 70/spl deg/C. The authors describe the fabrication process for SFRAM devices, provide performance data for discrete transistors measured to date, and show design criteria for a 64 kbit SFRAM.
File Size	81431
File Format	PDF
ISBN	0780345185
DOI	10.1109/NVMT.1998.723211
Language	English
Publisher	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Publisher Date	1998-06-24
Publisher Place	USA
Access Restriction	Subscribed
Rights Holder	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Subject Keyword	Nonvolatile memory Random access memory Ferroelectric films Ferroelectric materials FETs Capacitors Electrodes Semiconductivity Conductivity CMOS technology
Content Type	Text
Resource Type	Article

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