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| Content Provider | IEEE Xplore Digital Library |
|---|---|
| Author | Musumeci, S. Pagano, R. Raciti, A. Belverde, G. Guastella, C. Melito, M. |
| Copyright Year | 2003 |
| Description | Author affiliation: DIEES-ARIEL, Catania Univ., Italy (Musumeci, S.; Pagano, R.; Raciti, A.) |
| Abstract | This paper deals with a novel short circuit protection technique that is applied during fault under load (FUL) conditions occurring on IGBT devices. An experimental analysis of rugged IGBTs, which are submitted to FUL transients, has been performed dwelling upon the main stresses associated with the fault. In particular, the issues pertinent to the current transient are analysed, and the state-of-the-art regarding the protection circuit as appearing in literature is recalled and discussed. A novel circuitry is proposed aiming to strongly limit the peak of current deriving from a FUL transient, thus limiting the considerable energetic and thermal stresses onto the device. Besides, a theoretical analysis explaining the working mechanism of the proposed circuit has been carried out. Finally, the experimental results, which have been obtained by exploiting a suitable breadboard able to create FUL transients, confirm the validity and correctness of the proposed approach. |
| Sponsorship | IEEE Industrial Electronics Soc |
| Starting Page | 1733 |
| Ending Page | 1738 |
| File Size | 444871 |
| Page Count | 6 |
| File Format | |
| ISBN | 0780379063 |
| DOI | 10.1109/IECON.2003.1280319 |
| Language | English |
| Publisher | Institute of Electrical and Electronics Engineers, Inc. (IEEE) |
| Publisher Date | 2003-11-02 |
| Publisher Place | USA |
| Access Restriction | Subscribed |
| Rights Holder | Institute of Electrical and Electronics Engineers, Inc. (IEEE) |
| Subject Keyword | Insulated gate bipolar transistors Circuit faults Thermal stresses Voltage Transient analysis Performance analysis Power system protection Thermal resistance Circuit testing Capacitance |
| Content Type | Text |
| Resource Type | Article |
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