NDLI: High-throughput interpolation hardware architecture with coarse-grained reconfigurable datapaths for HEVC

Content Provider	IEEE Xplore Digital Library
Author	Machado Diniz, C. Shafique, M. Bampi, S. Henkel, J.
Copyright Year	2013
Description	Author affiliation: Dept. of Embedded Syst., Karlsruhe Inst. of Technol. (KIT), Karlsruhe, Germany (Machado Diniz, C.; Shafique, M.; Henkel, J.) \|\| Inst. of Inf., Fed. Univ. of Rio Grande do Sul (UFRGS), Porto Alegre, Brazil (Bampi, S.)
Abstract	Fractional-pel interpolation for motion estimation and motion compensation is one of the key computational hotspots in the new High Efficient Video Coding (HEVC) standard. This work presents a high-throughput interpolation hardware architecture to improve performance of HEVC encoding and decoding. It employs two acceleration engines for luma and chroma filtering, each with 12-pel-parallel coarse-grained reconfigurable interpolation datapaths. An adaptive scheduling scheme manages the operation of these interpolation datapaths in different ways depending upon the prediction unit (PU) size and the execution scenario (i.e. motion estimation or motion compensation). We have implemented our hardware architecture in 150 nm technology. Compared to state-of-the-art techniques [12], our architecture required 49% less hardware area, while processing QFHD (3840×2160) resolution @ 30 fps.
Starting Page	2091
Ending Page	2095
File Size	415155
Page Count	5
File Format	PDF
ISBN	9781479923410
DOI	10.1109/ICIP.2013.6738431
Language	English
Publisher	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Publisher Date	2013-09-15
Publisher Place	Australia
Access Restriction	Subscribed
Rights Holder	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Subject Keyword	Reconfigurable Datapaths HEVC Interpolation Filter Motion Estimation (ME) Motion Compensation (MC) Hardware Acceleration
Content Type	Text
Resource Type	Article

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