NDLI: Low-voltage on-chip cache architecture using heterogeneous cell sizes for high-performance processors

Content Provider	IEEE Xplore Digital Library
Author	Ghasemi, H.R. Draper, S.C. Nam Sung Kim
Copyright Year	2011
Description	Author affiliation: Department of Electrical and Computer Engineering, University of Wisconsin-Madison (Ghasemi, H.R.; Draper, S.C.; Nam Sung Kim)
Abstract	To date dynamic voltage/frequency scaling (DVFS) has been one of the most successful power-reduction techniques. However, ever-increasing process variability reduces the reliability of static random access memory (SRAM) at low voltages. This limits voltage scaling to a minimum operating voltage (VDDMIN). Larger SRAM cells, that are less sensitive to process variability, allow the use of lower VDDMIN. However, large-scale memory structures, e.g., the last-level cache (LLC) (that often determines the VDDMIN of the processor), cannot afford to use such large SRAM cells due to the die area constraint. In this paper we propose low-voltage LLC architectures that exploit 1) the DVFS characteristics of workloads running on high-performance processors, 2) the trade-off between SRAM cell size and VDDMIN, and 3) the fact that at lower voltage/frequency operating states the negative performance impact of having a smaller LLC capacity is reduced. Our proposed LLC architectures provide the same maximum performance and VDDMIN as the conventional architecture, while reducing the total LLC cell area by 15%–19% with negligible average runtime increase.
Starting Page	38
Ending Page	49
File Size	289059
Page Count	12
File Format	PDF
ISBN	9781424494323
ISSN	15300897
e-ISBN	9781424494354
DOI	10.1109/HPCA.2011.5749715
Language	English
Publisher	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Publisher Date	2011-02-12
Publisher Place	USA
Access Restriction	Subscribed
Rights Holder	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Subject Keyword	Computer architecture Microprocessors Random access memory Program processors Runtime System-on-a-chip Transistors
Content Type	Text
Resource Type	Article

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1	Ministry of Education (GoI), Department of Higher Education	Sanctioning Authority	https://www.education.gov.in/ict-initiatives
2	Indian Institute of Technology Kharagpur	Host Institute of the Project: The host institute of the project is responsible for providing infrastructure support and hosting the project	https://www.iitkgp.ac.in
3	National Digital Library of India Office, Indian Institute of Technology Kharagpur	The administrative and infrastructural headquarters of the project	Dr. B. Sutradhar bsutra@ndl.gov.in
4	Project PI / Joint PI	Principal Investigator and Joint Principal Investigators of the project	Dr. B. Sutradhar bsutra@ndl.gov.in Prof. Saswat Chakrabarti will be added soon
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