NDLI: Process and Circuit Optimization for Power Reduction Using DDC Transistors

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Process and Circuit Optimization for Power Reduction Using DDC Transistors

Content Provider	IEEE Xplore Digital Library
Author	Kidd, D.
Copyright Year	1981
Abstract	The Deeply Depleted Channel (DDC) transistor architecture offers 2 to 3 times improvement in body coefficient and 60 percent improvement in local mismatch in 55-nm technology, extending design techniques such as body biasing with voltage scaling to more recent technology nodes. This article presents a body bias architecture for adaptive correction of manufacturing variation, with less than 0.5 percent area penalty for the bias generators. Process monitors with digital readout independently detect p-channel MOS (PMOS) and n-channel MOS (NMOS) process windows. Fujitsu Semiconductor Limited offers DDC technology in its CS250S 55-nm production qualified process, and is currently in production with its first DDC product, a seventh-generation Milbeaut digital-camera processor that performs at twice the performance of the previous generation with 30 percent less power.
Sponsorship	IEEE Computer Society
Starting Page	54
Ending Page	62
Page Count	9
File Size	1173567
File Format	PDF
ISSN	02721732
Volume Number	34
Issue Number	2
Language	English
Publisher	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Publisher Date	2014-01-01
Publisher Place	U.S.A.
Access Restriction	One Nation One Subscription (ONOS)
Rights Holder	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Subject Keyword	Transistors Threshold voltage Manufacturing Logic gates Random access memory System-on-chip Performance evaluation Program processors Computer architecture built-in tests low-power design
Content Type	Text
Resource Type	Article
Subject	Electrical and Electronic Engineering Software Hardware and Architecture

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