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| Content Provider | IEEE Xplore Digital Library |
|---|---|
| Author | Govindarajan, R. Rengarajan, S. |
| Copyright Year | 1996 |
| Description | Author affiliation: Dept. of Comput. Sci. & Autom., Indian Inst. of Sci., Bangalore, India (Govindarajan, R.) |
| Abstract | In this paper we discuss a method to perform compile-time buffer allocation, allowing efficient buffer sharing among the arcs of a special form of dataflow graphs-known as regular stream flow graphs-commonly used in Digital Signal Processing applications. We relate the buffer sharing problem to that of finding independent sets in weighted circular arc graph. An important difference between the traditional graph coloring/register allocation problem and our buffer sharing problem is that in our problem the aim is to minimize the sum of the weights of the independent sets, rather than the number of independent sets. We present a heuristic algorithm and experiment it on a large number of randomly generated regular dataflow graphs as well as a few DSP applications. It is observed that the heuristic algorithm performs well, reducing the buffer requirement by 14.3% on the average. Also, we observe that buffer requirement achieved by the heuristic algorithm is within 2.1% from the lower bound. |
| Starting Page | 419 |
| Ending Page | 424 |
| File Size | 580873 |
| Page Count | 6 |
| File Format | |
| ISBN | 0818675578 |
| DOI | 10.1109/HIPC.1996.565857 |
| Language | English |
| Publisher | Institute of Electrical and Electronics Engineers, Inc. (IEEE) |
| Publisher Date | 1996-12-19 |
| Publisher Place | India |
| Access Restriction | Subscribed |
| Rights Holder | Institute of Electrical and Electronics Engineers, Inc. (IEEE) |
| Subject Keyword | Intelligent networks Digital signal processing Heuristic algorithms Signal processing algorithms Flow graphs Registers Supercomputers Computer science education Computer science Automation |
| Content Type | Text |
| Resource Type | Article |
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