NDLI: A multithreaded architecture for the efficient execution of vector computations within a loop using status field

Content Provider	IEEE Xplore Digital Library
Author	Youn, S.D. Chung, K.D.
Copyright Year	1996
Description	Author affiliation: Dept. of Comput. Sci., Pukyong Nat. Univ., Pusan, South Korea (Youn, S.D.)
Abstract	This paper presents the design of a high performance MULVEC(M_U_L_tithreaded architecture for the V_E_ctor C_omputations), as a building block of massively parallel processing systems. MULVEC comes from the synthesis of the dataflow model and the extant superscalar RISC microprocessor. MULVEC reduces, using a vector wait queue and status field of each vector data, the number of synchronization, context switching, network traffic, and so on in case of repeated vector computations within the same thread segment. And if vector operand in one statement is more than three, MULVEC can be computed by non-strict method. After program having been simulated on the SPARC V9(super scalar bit RISC microprocessor), the performance (execution time of example program) of uniprocessor and MULVEC according to the different number of nodes are analyzed. The performance of MULVEC according to the different number of nodes are analyzed for the several programs.
Starting Page	343
Ending Page	350
File Size	626836
Page Count	8
File Format	PDF
ISBN	0818675578
DOI	10.1109/HIPC.1996.565845
Language	English
Publisher	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Publisher Date	1996-12-19
Publisher Place	India
Access Restriction	Subscribed
Rights Holder	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Subject Keyword	Reduced instruction set computing Microprocessors Performance analysis Parallel processing Network synthesis Telecommunication traffic Traffic control Computer networks Yarn Computational modeling
Content Type	Text
Resource Type	Article

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