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| Content Provider | IEEE Xplore Digital Library |
|---|---|
| Author | Delgado, M. Kofuji, S. |
| Copyright Year | 1996 |
| Description | Author affiliation: Lab. of Integrated Syst.-Polytech. Sch., Sao Paulo Univ., Brazil (Delgado, M.) |
| Abstract | This paper shows a new hardware solution for implementing barrier synchronization in 2D-mesh multicomputers. The synchronization process is executed in n-1 sequential stages where n is the largest dimension of the nxm mesh configuration. Each stage establishes simultaneous communication with maximum 4 nodes through additional wired-AND wires, allowing the propagation of information among the adjacent cells every time. This solution presents the following characteristics: (a) fast barrier synchronization, (b) allows that any subset of nodes participate in each barrier whenever sequential barriers are considered, and (c) allows simultaneous execution of multiple barriers whenever subsets of nodes belonging to non-overlapping rectangles are considered. The control logic and number of wired-AND wires are the same per node. Therefore, the system size is easily increased, being only limited by the expansion capacity of the 2D-mesh network. Analytical results indicate that the new approach should perform almost as well as efficient barrier synchronizers. |
| Starting Page | 368 |
| Ending Page | 373 |
| File Size | 568877 |
| Page Count | 6 |
| File Format | |
| ISBN | 0818675578 |
| DOI | 10.1109/HIPC.1996.565849 |
| Language | English |
| Publisher | Institute of Electrical and Electronics Engineers, Inc. (IEEE) |
| Publisher Date | 1996-12-19 |
| Publisher Place | India |
| Access Restriction | Subscribed |
| Rights Holder | Institute of Electrical and Electronics Engineers, Inc. (IEEE) |
| Subject Keyword | Hardware Wires Logic Laboratories Performance analysis Parallel algorithms Delay Data structures Costs Mechanical factors |
| Content Type | Text |
| Resource Type | Article |
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