NDLI: Thermal-aware high-level synthesis based on network flow method

Content Provider	IEEE Xplore Digital Library
Author	Pilok Lim Taewhan Kim
Copyright Year	2006
Description	Author affiliation: Seoul Nat. Univ., Seoul (Pilok Lim; Taewhan Kim)
Abstract	Lowering down the chip temperature is becoming one of the important design considerations, since temperature adversely and seriously affects many of design qualities, such as reliability, performance and leakage power of chip, and also increases the packaging cost. In this work, we address a new problem of thermal-aware module binding in high-level synthesis, in which the objective is to minimize the peak temperature of the chip. The two key contributions are (1) to solve the binding problem with the primary objective of minimizing the 'peak' switched capacitance of modules and the secondary objective of minimizing the 'total' switched capacitance of modules and (2) to control the switched capacitances with respect to the floorplan of modules in a way to minimize the 'peak' heat diffusion between modules. For (1), our proposed thermal-aware binding algorithm, called TA-b, formulates the thermal-aware binding problem into a problem of repeated utilization of network flow method, and solve it effectively. For (2), TA-b is extended, called TA-bf, to take into account a floorplan information, if exists, of modules to be practically effective. From experiments using a set of benchmarks, it is shown that TA-bf is able to use 10.1degC and 11.8degC lower peak temperature on the average, compared to that of the conventional low-power and thermal- aware methods, which target to minimizing total switched capacitance only ([18]) and to minimizing peak switched capacitance only ([16]), respectively.
Starting Page	124
Ending Page	129
File Size	176159
Page Count	6
File Format	PDF
ISBN	1595933700
DOI	10.1145/1176254.1176285
Language	English
Publisher	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Publisher Date	2006-10-22
Publisher Place	South Korea
Access Restriction	Subscribed
Rights Holder	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Subject Keyword	High level synthesis Capacitance Energy consumption Equations Temperature measurement Iterative algorithms Computer science Computer network reliability Packaging Costs temperature binding power consumption
Content Type	Text
Resource Type	Article

Sl.	Authority	Responsibilities	Communication Details
1	Ministry of Education (GoI), Department of Higher Education	Sanctioning Authority	https://www.education.gov.in/ict-initiatives
2	Indian Institute of Technology Kharagpur	Host Institute of the Project: The host institute of the project is responsible for providing infrastructure support and hosting the project	https://www.iitkgp.ac.in
3	National Digital Library of India Office, Indian Institute of Technology Kharagpur	The administrative and infrastructural headquarters of the project	Dr. B. Sutradhar bsutra@ndl.gov.in
4	Project PI / Joint PI	Principal Investigator and Joint Principal Investigators of the project	Dr. B. Sutradhar bsutra@ndl.gov.in Prof. Saswat Chakrabarti will be added soon
5	Website/Portal (Helpdesk)	Queries regarding NDLI and its services	support@ndl.gov.in
6	Contents and Copyright Issues	Queries related to content curation and copyright issues	content@ndl.gov.in
7	National Digital Library of India Club (NDLI Club)	Queries related to NDLI Club formation, support, user awareness program, seminar/symposium, collaboration, social media, promotion, and outreach	clubsupport@ndl.gov.in
8	Digital Preservation Centre (DPC)	Assistance with digitizing and archiving copyright-free printed books	dpc@ndl.gov.in
9	IDR Setup or Support	Queries related to establishment and support of Institutional Digital Repository (IDR) and IDR workshops	idr@ndl.gov.in

Thermal-aware high-level synthesis based on network flow method

Thermal-aware high-level synthesis based on network flow method (2006)

Fast high-level power estimation for control-flow intensive designs

Peak temperature control and leakage reduction during binding in high level synthesis

Thermal-aware lifetime reliability in multicore systems

Thermal aware AND-OR-XOR network synthesis

TAPHS: thermal-aware unified physical-level and high-level synthesis

Evaluation of thermal-aware design techniques for microprocessors

Restricted Chaining and Fragmentation Techniques in Power Aware High Level Synthesis

Thermal-aware high-level synthesis based on network flow method

Similar Documents

Thermal-aware high-level synthesis based on network flow method

Thermal-aware high-level synthesis based on network flow method (2006)

Fast high-level power estimation for control-flow intensive designs

Peak temperature control and leakage reduction during binding in high level synthesis

Thermal-aware lifetime reliability in multicore systems

Thermal aware AND-OR-XOR network synthesis

TAPHS: thermal-aware unified physical-level and high-level synthesis

Evaluation of thermal-aware design techniques for microprocessors

Restricted Chaining and Fragmentation Techniques in Power Aware High Level Synthesis

Thermal-aware high-level synthesis based on network flow method