NDLI: Integration difficulties and limitations in sub-0.25 /spl mu/m CMOS and CMOS-based technologies

Content Provider	IEEE Xplore Digital Library
Author	Deferm, L. Badenes, G.
Copyright Year	1999
Description	Author affiliation: Silicon Device & Process Integration Div., IMEC, Leuven, Belgium (Deferm, L.)
Abstract	Market demands, which require increased functionality at lower costs are driving the development of high performance CMOS technologies with very high integration density. These demands are pushing the continuous scaling down of technologies and are resulting in a progressive acceleration of the rate of introduction of new technology generations. Current research and development activities in CMOS technology are focused on scaling the 0.25 /spl mu/m CMOS technology generation down to 0.18 /spl mu/m or even 0.13 /spl mu/m dimensions. While some of the process modules can be scaled down in a conventional way, in some cases severe limitations are reached and it is necessary to introduce major modifications to the process flow. In this paper we will present an overview of the main considerations to be kept in mind when scaling down to a 0.18 pm CMOS technology generation.
Starting Page	399
Ending Page	406
File Size	982709
Page Count	8
File Format	PDF
ISBN	0780352351
DOI	10.1109/ICMEL.2000.838721
Language	English
Publisher	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Publisher Date	2000-05-14
Publisher Place	Yugoslavia
Access Restriction	Subscribed
Rights Holder	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Subject Keyword	CMOS technology Lithography Costs Resists Reproducibility of results CMOS process Etching Silicon Production Manufacturing processes
Content Type	Text
Resource Type	Article

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