NDLI: Silicon measurements of characteristics for passgate/pull-down/pull-up MOSs and search MOS in a 28 nm HKMG TCAM bitcell

Content Provider	IEEE Xplore Digital Library
Author	Nii, K. Yamaguchi, K. Yabuuchi, M. Watanabe, N. Hasegawa, T. Yoshida, S. Okagaki, T. Yokota, M. Onozawa, K.
Copyright Year	2015
Description	Author affiliation: Renesas Electron. Corp., Tokyo, Japan (Nii, K.; Yamaguchi, K.; Yabuuchi, M.; Watanabe, N.; Hasegawa, T.; Yoshida, S.; Okagaki, T.; Yokota, M.; Onozawa, K.)
Abstract	Test structures for measuring characteristics of MOS components in 28 nm high-k metal-gate (HKMG) Ternary Content-Addressable memory (TCAM) bitcell are implemented. Proposed TCAM bitcell are including pull-down (PD) and pass-gate (PG) NMOSs, pull-up (PU) PMOSs and search NMOSs, which are built up based on standard 6T SRAM bitcell. It can achieve the small area but symmetrical layout could not be implemented. Each MOS characteristic is measured by test structure and observed over 20 mV $V_{t}$ offset for each PD and PG NMOS pairs due to asymmetrical layout, whereas there is no difference in PU-PMOS pair. From measurement results we estimate the bit error rates on the supply voltage for TCAM array and predict that the TCAM $V_{min}$ for read-operation becomes worse by 42 mV at 5.3-sigma condition compared to that of standard SRAM array. Based on measured bitcell characteristics we designed and fabricated 80-Mbit TCAM test chips with appropriate redundancies, achieving below 740 mV $V_{min}$ at 250 MHz operation at 25°C and 85°C.
Starting Page	200
Ending Page	203
File Size	1820151
Page Count	4
File Format	PDF
ISBN	9781479983025
ISSN	10719032
e-ISBN	9781479983049
DOI	10.1109/ICMTS.2015.7106140
Language	English
Publisher	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Publisher Date	2015-03-23
Publisher Place	USA
Access Restriction	Subscribed
Rights Holder	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Subject Keyword	Random access memory Logic gates MOS devices Arrays Semiconductor device measurement High K dielectric materials layout dependency effect Ternary Content-Addressable Memory TCAM 6T SRAM bitcell 28nm metal-gate Vmin bit-error-rate read margin write margin redundancy
Content Type	Text
Resource Type	Article

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4	Project PI / Joint PI	Principal Investigator and Joint Principal Investigators of the project	Dr. B. Sutradhar bsutra@ndl.gov.in Prof. Saswat Chakrabarti will be added soon
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