NDLI: Sensitivity-independent extraction of Vth variation utilizing log-normal delay distribution

Content Provider	IEEE Xplore Digital Library
Author	Mahfuzul Islam, A.K.M. Onodera, H.
Copyright Year	2015
Description	Author affiliation: Grad. Sch. of Inf., Kyoto Univ., Kyoto, Japan (Mahfuzul Islam, A.K.M.; Onodera, H.)
Abstract	We propose an area-efficient and low-cost extraction methodology of $V_{th}$ variation which utilizes the exponential relationship of gate delay to $V_{th}$ variation. The exponential relationship is achieved by operating the DUT in the weak inversion region. Utilizing a previously proposed pass-gate based topology-reconfigurable ring oscillator, the weak inversion operation of a specific gate is achieved while maintaining a much higher supply voltage for the overall circuit. Area-efficiency is achieved by altering the individual gate topology and measuring for each topology. Based on a pass-gate inserted inverter delay model, the relationship of delay variation to $V_{th}$ variation is expressed using the body effect and DIBL coefficients. Thus, the proposed method does not require any sensitivity calculation. $V_{th}$ variation is then extracted from the measured delay distributions directly. A test chip containing three different sizes of DUTs are fabricated in a 65-nm bulk CMOS process. $V_{th}$ variation of nMOSFET and pMOSFET for three different DUT sizes are successfully extracted. The methodology is suitable for low-cost, area-efficient and all-digital measurement of $V_{th}$ variation.
Starting Page	212
Ending Page	217
File Size	1934418
Page Count	6
File Format	PDF
ISBN	9781479983025
ISSN	10719032
e-ISBN	9781479983049
DOI	10.1109/ICMTS.2015.7106155
Language	English
Publisher	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Publisher Date	2015-03-23
Publisher Place	USA
Access Restriction	Subscribed
Rights Holder	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Subject Keyword	Delays Nonhomogeneous media Logic gates MOSFET circuits Transistors Semiconductor device measurement Oscillators
Content Type	Text
Resource Type	Article

Sl.	Authority	Responsibilities	Communication Details
1	Ministry of Education (GoI), Department of Higher Education	Sanctioning Authority	https://www.education.gov.in/ict-initiatives
2	Indian Institute of Technology Kharagpur	Host Institute of the Project: The host institute of the project is responsible for providing infrastructure support and hosting the project	https://www.iitkgp.ac.in
3	National Digital Library of India Office, Indian Institute of Technology Kharagpur	The administrative and infrastructural headquarters of the project	Dr. B. Sutradhar bsutra@ndl.gov.in
4	Project PI / Joint PI	Principal Investigator and Joint Principal Investigators of the project	Dr. B. Sutradhar bsutra@ndl.gov.in Prof. Saswat Chakrabarti will be added soon
5	Website/Portal (Helpdesk)	Queries regarding NDLI and its services	support@ndl.gov.in
6	Contents and Copyright Issues	Queries related to content curation and copyright issues	content@ndl.gov.in
7	National Digital Library of India Club (NDLI Club)	Queries related to NDLI Club formation, support, user awareness program, seminar/symposium, collaboration, social media, promotion, and outreach	clubsupport@ndl.gov.in
8	Digital Preservation Centre (DPC)	Assistance with digitizing and archiving copyright-free printed books	dpc@ndl.gov.in
9	IDR Setup or Support	Queries related to establishment and support of Institutional Digital Repository (IDR) and IDR workshops	idr@ndl.gov.in

Inhomogeneous ring oscillator for WID variability and RTN characterization

Reconfigurable delay cell for area-efficient implementation of on-chip MOSFET monitor schemes

An impact of process variation on supply voltage dependence of logic path delay variation

In-situ variability characterization of individual transistors using topology-reconfigurable ring oscillators

Circuits to measure the delay variability of MOSFETs

Threshold voltage extraction circuit for low voltage CMOS design using basic long-channel MOSFET

Scaling of serially-connected MOSFET chains

Switching and conducting performance of SiC-JFET and ESBT against MOSFET and IGBT

Delay model for static CMOS complex gates

Sensitivity-independent extraction of Vth variation utilizing log-normal delay distribution

Similar Documents

Inhomogeneous ring oscillator for WID variability and RTN characterization

Reconfigurable delay cell for area-efficient implementation of on-chip MOSFET monitor schemes

An impact of process variation on supply voltage dependence of logic path delay variation

In-situ variability characterization of individual transistors using topology-reconfigurable ring oscillators

Circuits to measure the delay variability of MOSFETs

Threshold voltage extraction circuit for low voltage CMOS design using basic long-channel MOSFET

Scaling of serially-connected MOSFET chains

Switching and conducting performance of SiC-JFET and ESBT against MOSFET and IGBT

Delay model for static CMOS complex gates

Sensitivity-independent extraction of Vth variation utilizing log-normal delay distribution