NDLI: On the combined impact of soft and medium gate oxide breakdown and process variability on the parametric figures of SRAM components

Content Provider	IEEE Xplore Digital Library
Author	Hua Wang Miranda, M. Catthoor, F. Dehaene, W.
Copyright Year	2006
Description	Author affiliation: IMEC, Leuven (Hua Wang; Miranda, M.; Catthoor, F.)
Abstract	The effect of gate oxide breakdown has long been studied in the context of device functional failure in the past. As technology node scales down to very deep submicron (VDSM) era, such an effect starts to influence the performance and power consumption of digital circuits within their lifetime. Meanwhile, process variability like threshold voltage shift due to e.g., device dopant fluctuation and/or line edge roughness effects also leads to significant shift of the parametric figures for performance and energy of these circuits at sub 100nm era. Further scaling will definitely lead to the co-existence of both effects in a single circuit. In this paper, we present the experimental analysis on the impact combining gate oxide breakdown and process variability on the energy and delay figures of SRAM cell and sense amplifier. Hspice simulations at 65nm technology node indicate a significantly larger shift in both energy and delay of these components than in the cases with either single effect when using the thinner oxide found in 45/32 nm technologies. The actual behavior of the circuits under such a situation becomes more difficult to predict and control, thus bringing a huge challenge to a successful design in the VDSM era
Sponsorship	IEEE Comput. Soc. Test Technol. Tech. Council
Starting Page	6
Ending Page	76
File Size	400966
Page Count	71
File Format	PDF
ISBN	0769525725
ISSN	10874852
DOI	10.1109/MTDT.2006.23
Language	English
Publisher	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Publisher Date	2006-08-02
Publisher Place	Taiwan
Access Restriction	Subscribed
Rights Holder	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Subject Keyword	Electric breakdown Random access memory Breakdown voltage Threshold voltage Fluctuations Delay effects Degradation Energy consumption Digital circuits Circuit simulation
Content Type	Text
Resource Type	Article

Sl.	Authority	Responsibilities	Communication Details
1	Ministry of Education (GoI), Department of Higher Education	Sanctioning Authority	https://www.education.gov.in/ict-initiatives
2	Indian Institute of Technology Kharagpur	Host Institute of the Project: The host institute of the project is responsible for providing infrastructure support and hosting the project	https://www.iitkgp.ac.in
3	National Digital Library of India Office, Indian Institute of Technology Kharagpur	The administrative and infrastructural headquarters of the project	Dr. B. Sutradhar bsutra@ndl.gov.in
4	Project PI / Joint PI	Principal Investigator and Joint Principal Investigators of the project	Dr. B. Sutradhar bsutra@ndl.gov.in Prof. Saswat Chakrabarti will be added soon
5	Website/Portal (Helpdesk)	Queries regarding NDLI and its services	support@ndl.gov.in
6	Contents and Copyright Issues	Queries related to content curation and copyright issues	content@ndl.gov.in
7	National Digital Library of India Club (NDLI Club)	Queries related to NDLI Club formation, support, user awareness program, seminar/symposium, collaboration, social media, promotion, and outreach	clubsupport@ndl.gov.in
8	Digital Preservation Centre (DPC)	Assistance with digitizing and archiving copyright-free printed books	dpc@ndl.gov.in
9	IDR Setup or Support	Queries related to establishment and support of Institutional Digital Repository (IDR) and IDR workshops	idr@ndl.gov.in

Impact of Random Soft Oxide Breakdown on SRAM Energy/Delay Drift

Gate oxide multiple soft breakdown (Multi-SBD) impact on CMOS inverter

On the Combined Impact of Soft and Medium Gate Oxide

Power-switch gate-oxide breakdown tolerance techniques for power-gated SRAM

Experimental verification of SRAM cell functionality after hard and soft gate oxide breakdowns

Variability resilient low-power 7T-SRAM design for nano-scaled technologies

Impact of gate-oxide breakdown on power-gated SRAM

Soft Oxide Breakdown impact on the functionality of a 40 nm SRAM memory

SRAM Yield Sensitivity to Supply Voltage Fluctuations and Its Implications on Vmin

On the combined impact of soft and medium gate oxide breakdown and process variability on the parametric figures of SRAM components

Similar Documents

Impact of Random Soft Oxide Breakdown on SRAM Energy/Delay Drift

Gate oxide multiple soft breakdown (Multi-SBD) impact on CMOS inverter

On the Combined Impact of Soft and Medium Gate Oxide

Power-switch gate-oxide breakdown tolerance techniques for power-gated SRAM

Experimental verification of SRAM cell functionality after hard and soft gate oxide breakdowns

Variability resilient low-power 7T-SRAM design for nano-scaled technologies

Impact of gate-oxide breakdown on power-gated SRAM

Soft Oxide Breakdown impact on the functionality of a 40 nm SRAM memory

SRAM Yield Sensitivity to Supply Voltage Fluctuations and Its Implications on Vmin

On the combined impact of soft and medium gate oxide breakdown and process variability on the parametric figures of SRAM components