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| Content Provider | IEEE Xplore Digital Library |
|---|---|
| Author | Ding-Ming Kwai Yung-Fa Chou Meng-Fan Chang Su-Meng Yang Ding-Sheng Chen Min-Chung Hsu Yu-Zhen Liao Shiao-Yi Lin Yu-Ling Sung Chia-Hsin Lee Hsin-Kun Hsu |
| Copyright Year | 2006 |
| Description | Author affiliation: Intellectual Property Libr. Co., Hsinchu (Ding-Ming Kwai; Yung-Fa Chou; Meng-Fan Chang; Su-Meng Yang; Ding-Sheng Chen; Min-Chung Hsu; Yu-Zhen Liao; Shiao-Yi Lin; Yu-Ling Sung; Chia-Hsin Lee; Hsin-Kun Hsu) |
| Abstract | We present a ROM compiler programmable from via 1 to via n - 2, where n is the number of metal layers. The layer on which the code via is landed can be selected by the user. With the coding being able to take place as close to the topmost metal as possible, the turnaround time for a revision is shortened. In this paper, we discuss the array assembly scheme and its impacts on the design considerations by the choice of strapping period |
| Sponsorship | IEEE Comput. Soc. Test Technol. Tech. Council |
| Starting Page | 28 |
| Ending Page | 33 |
| File Size | 434999 |
| Page Count | 6 |
| File Format | |
| ISBN | 0769525725 |
| ISSN | 10874852 |
| DOI | 10.1109/MTDT.2006.14 |
| Language | English |
| Publisher | Institute of Electrical and Electronics Engineers, Inc. (IEEE) |
| Publisher Date | 2006-08-02 |
| Publisher Place | Taiwan |
| Access Restriction | Subscribed |
| Rights Holder | Institute of Electrical and Electronics Engineers, Inc. (IEEE) |
| Subject Keyword | Read only memory Program processors Assembly Application specific integrated circuits Logic circuits CMOS process Intellectual property Libraries Design engineering Costs |
| Content Type | Text |
| Resource Type | Article |
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