NDLI: A 1kb 9T subthreshold SRAM with bit-interleaving scheme in 65nm CMOS

Content Provider	IEEE Xplore Digital Library
Author	Ming-Hung Chang Yi-Te Chiu Shu-Lin Lai Wei Hwang
Copyright Year	2011
Description	Author affiliation: Department of Electronics Engineering & Institute of Electronics, and Microelectronics and Information System Research Center (MIRC), National Chiao-Tung University, Hsinchu 300, Taiwan (Ming-Hung Chang; Yi-Te Chiu; Shu-Lin Lai; Wei Hwang)
Abstract	Subthreshold SRAM is a significant approach to reduce power consumption in energy-constrained SoC design. For the ultra-low power consideration, the primary concerns of SRAM are stability and reliability instead of performance. In this paper, the proposed 9T bit-cell enhances write ability by cutting off the positive feedback loop of inverter pair. In the read mode, the isolated read path and storage node enlarge the read SNM. Besides, a 9T subthreshold SRAM is proposed to enable implementation of bit-interleaving structure which achieves soft-error tolerance. The proposed SRAM is able to operate at a voltage as low as 0.3V. One extra virtual ground (VVSS) line is used to reduce the bit-line leakage to ensure the data can be read successfully. A 1kb bit-interleaved 9T SRAM is implemented in UMC 65nm 1P10M CMOS technology to verify the proposed scheme, which operates at the minimum energy point (0.3V) with 5.824pJ energy consumption for one write and one read operation.
Starting Page	291
Ending Page	296
File Size	1741473
Page Count	6
File Format	PDF
ISBN	9781612846583
e-ISBN	9781612846606
e-ISBN	9781612846590
DOI	10.1109/ISLPED.2011.5993652
Language	English
Publisher	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Publisher Date	2011-08-01
Publisher Place	Japan
Access Restriction	Subscribed
Rights Holder	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Subject Keyword	Random access memory Transistors Delay Reliability Arrays Error correction codes Decoding bit-interleaving scheme ultra-low power subthreshold SRAM
Content Type	Text
Resource Type	Article

Sl.	Authority	Responsibilities	Communication Details
1	Ministry of Education (GoI), Department of Higher Education	Sanctioning Authority	https://www.education.gov.in/ict-initiatives
2	Indian Institute of Technology Kharagpur	Host Institute of the Project: The host institute of the project is responsible for providing infrastructure support and hosting the project	https://www.iitkgp.ac.in
3	National Digital Library of India Office, Indian Institute of Technology Kharagpur	The administrative and infrastructural headquarters of the project	Dr. B. Sutradhar bsutra@ndl.gov.in
4	Project PI / Joint PI	Principal Investigator and Joint Principal Investigators of the project	Dr. B. Sutradhar bsutra@ndl.gov.in Prof. Saswat Chakrabarti will be added soon
5	Website/Portal (Helpdesk)	Queries regarding NDLI and its services	support@ndl.gov.in
6	Contents and Copyright Issues	Queries related to content curation and copyright issues	content@ndl.gov.in
7	National Digital Library of India Club (NDLI Club)	Queries related to NDLI Club formation, support, user awareness program, seminar/symposium, collaboration, social media, promotion, and outreach	clubsupport@ndl.gov.in
8	Digital Preservation Centre (DPC)	Assistance with digitizing and archiving copyright-free printed books	dpc@ndl.gov.in
9	IDR Setup or Support	Queries related to establishment and support of Institutional Digital Repository (IDR) and IDR workshops	idr@ndl.gov.in

A 1kb 9T subthreshold SRAM with bit-interleaving scheme in 65nm CMOS

Design and Iso-Area $V_{min}$ Analysis of 9T Subthreshold SRAM With Bit-Interleaving Scheme in 65-nm CMOS

64-bits low power CMOS SRAM by using 9T cell and charge recycling scheme

A 0.32V, 55fJ per bit access energy, CMOS 65nm bit-interleaved SRAM with radiation Soft Error tolerance

Design and iso-area vmin analysis of 9t subthreshold sram with bit-interleaving scheme in 65-nm cmos.

A 32 kb 10T Sub-Threshold SRAM Array With Bit-Interleaving and Differential Read Scheme in 90 nm CMOS

A 0.33-V, 500-kHz, 3.94-$muhbox{W}$ 40-nm 72-Kb 9T Subthreshold SRAM With Ripple Bit-Line Structure and Negative Bit-Line Write-Assist

A 65nm SRAM achieving 250mV retention and 350mV, 1MHz, 55fJ/bit access energy, with bit-interleaved radiation Soft Error tolerance

An ultra low energy 9T half-select-free subthreshold SRAM bitcell

A 1kb 9T subthreshold SRAM with bit-interleaving scheme in 65nm CMOS

Similar Documents

A 1kb 9T subthreshold SRAM with bit-interleaving scheme in 65nm CMOS

Design and Iso-Area $V_{min}$ Analysis of 9T Subthreshold SRAM With Bit-Interleaving Scheme in 65-nm CMOS

64-bits low power CMOS SRAM by using 9T cell and charge recycling scheme

A 0.32V, 55fJ per bit access energy, CMOS 65nm bit-interleaved SRAM with radiation Soft Error tolerance

Design and iso-area vmin analysis of 9t subthreshold sram with bit-interleaving scheme in 65-nm cmos.

A 32 kb 10T Sub-Threshold SRAM Array With Bit-Interleaving and Differential Read Scheme in 90 nm CMOS

A 0.33-V, 500-kHz, 3.94-$muhbox{W}$ 40-nm 72-Kb 9T Subthreshold SRAM With Ripple Bit-Line Structure and Negative Bit-Line Write-Assist

A 65nm SRAM achieving 250mV retention and 350mV, 1MHz, 55fJ/bit access energy, with bit-interleaved radiation Soft Error tolerance

An ultra low energy 9T half-select-free subthreshold SRAM bitcell

A 1kb 9T subthreshold SRAM with bit-interleaving scheme in 65nm CMOS