NDLI: SAT-based capture-power reduction for at-speed broadcast-scan-based test compression architectures

Content Provider	IEEE Xplore Digital Library
Author	Kochte, M.A. Miyase, K. Wen, X. Kajihara, S. Yamato, Y. Enokimoto, K. Wunderlich, H.
Copyright Year	2011
Description	Author affiliation: ITI, University of Stuttgart, Stuttgart, Germany (Wunderlich, H.) \|\| Fukuoka Industry, Science and Technology Foundation, Fukuoka, Japan (Yamato, Y.) \|\| Kyushu Institute of Technology, Iizuka, Japan (Kochte, M.A.; Miyase, K.; Wen, X.; Kajihara, S.; Enokimoto, K.)
Abstract	Excessive power dissipation during VLSI testing results in over-testing, yield loss and heat damage of the device. For low power devices with advanced power management features and more stringent power budgets, power-aware testing is even more mandatory. Effective and efficient test set postprocessing techniques based on X-identification and power-aware X-filling have been proposed for external and embedded deterministic test. This work proposes a novel X-filling algorithm for combinational and broadcast-scan-based test compression schemes which have great practical significance. The algorithm ensures compressibility of test cubes using a SAT-based check. Compared to methods based on topological justification, the solution space of the compressed test vector is not pruned early during the search. Thus, this method allows much more precise low-power X-filling of test vectors. Experiments on benchmark and industrial circuits show the applicability to capture-power reduction during scan testing.
Starting Page	33
Ending Page	38
File Size	430077
Page Count	6
File Format	PDF
ISBN	9781612846583
e-ISBN	9781612846606
e-ISBN	9781612846590
DOI	10.1109/ISLPED.2011.5993600
Language	English
Publisher	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Publisher Date	2011-08-01
Publisher Place	Japan
Access Restriction	Subscribed
Rights Holder	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Subject Keyword	Flip-flops Automatic test pattern generation Integrated circuit modeling Switches Circuit faults Logic gates ATPG Low capture-power test X-filling
Content Type	Text
Resource Type	Article

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4	Project PI / Joint PI	Principal Investigator and Joint Principal Investigators of the project	Dr. B. Sutradhar bsutra@ndl.gov.in Prof. Saswat Chakrabarti will be added soon
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