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| Content Provider | IEEE Xplore Digital Library |
|---|---|
| Author | Kai-Chiang Wu Marculescu, D. Ming-Chao Lee Shih-Chieh Chang |
| Copyright Year | 2011 |
| Description | Author affiliation: Department of Electrical and Computer Engineering, Carnegie Mellon University, Pittsburgh, PA, USA (Kai-Chiang Wu; Marculescu, D.) || Department of Computer Science, National Tsing Hua University, Hsinchu, Taiwan (Ming-Chao Lee; Shih-Chieh Chang) |
| Abstract | Device aging, which causes significant loss on circuit performance and lifetime, has been a main factor in reliability degradation of nanoscale designs. Aggressive technology scaling trends, such as thinner gate oxide without proportional downscaling of supply voltage, necessitate an aging-aware analysis and optimization flow in the early design stages. Since PMOS sleep transistors in power-gated circuits suffer from static NBTI during active mode and age very rapidly, the aging of power-gated circuits should be explicitly addressed. In this paper, for power-gated circuits, we present a novel methodology for analyzing and mitigating NBTI-induced performance degradation. Aging effects on both logic networks and sleep transistors are jointly considered for accurate analysis. By introducing 25% redundant sleep transistors with reverse body bias applied, the proposed methodology can significantly mitigate the long-term performance degradation and thus extend the circuit lifetime by 3X. |
| Starting Page | 139 |
| Ending Page | 144 |
| File Size | 505186 |
| Page Count | 6 |
| File Format | |
| ISBN | 9781612846583 |
| e-ISBN | 9781612846606 |
| e-ISBN | 9781612846590 |
| DOI | 10.1109/ISLPED.2011.5993626 |
| Language | English |
| Publisher | Institute of Electrical and Electronics Engineers, Inc. (IEEE) |
| Publisher Date | 2011-08-01 |
| Publisher Place | Japan |
| Access Restriction | Subscribed |
| Rights Holder | Institute of Electrical and Electronics Engineers, Inc. (IEEE) |
| Subject Keyword | Degradation Aging Transistors Switching circuits Logic gates Integrated circuit modeling Mathematical model Reverse body bias Leakage NBTI Power gating |
| Content Type | Text |
| Resource Type | Article |
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