NDLI: A GHz-class charge recovery logic

Content Provider	IEEE Xplore Digital Library
Author	Sathe, V.S. Papaefthymiou, M.C. Ziesler, C.H.
Copyright Year	2005
Description	Author affiliation: Dept. of Electr. Eng. & Comput. Sci.,, Michigan Univ., Ann Arbor, MI, USA (Sathe, V.S.; Papaefthymiou, M.C.)
Abstract	This paper describes Boost Logic, a logic family which relies on voltage scaling, gate overdrive, and energy recovery, to achieve high energy efficiency at GHz frequencies. The key feature of our design is an energy recovering "boost" stage that provides a high gate overdrive to an aggressively voltage-scaled logic at near-threshold supply voltage. We have evaluated Boost Logic through post-layout simulation of an 8-bit carry-save multiplier in a 0.13/spl mu/m CMOS process with V/sub th/=340mV. At 1.6GHz and 1.3V supply voltage, the Boost multiplier dissipates 8.11pJ per computation, yielding 68% energy savings over its pipelined, voltage-scaled static CMOS counterpart. Using low V/sub th/ devices, the Boost Logic multiplier has been verified to operate at 2GHz with a 1.25V voltage supply and 8.50pJ energy dissipation per cycle.
Sponsorship	ACM SIGDA IEEE Circuits and Syst. Soc
Starting Page	91
Ending Page	94
File Size	830299
Page Count	4
File Format	PDF
ISBN	1595931376
DOI	10.1109/LPE.2005.195492
Language	English
Publisher	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Publisher Date	2005-08-08
Publisher Place	USA
Access Restriction	Subscribed
Rights Holder	Association for Computing Machinery, Inc. (ACM)
Subject Keyword	CMOS logic circuits Frequency Logic devices Dynamic voltage scaling Threshold voltage Pipeline processing Permission Logic gates Energy efficiency Logic design
Content Type	Text
Resource Type	Article

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