NDLI: ParIS: a parameterizable interconnect switch for networks-on-chip

Content Provider	IEEE Xplore Digital Library
Author	Zeferino, C.A. Santo, F.G.M.E. Susin, A.A.
Copyright Year	2004
Description	Author affiliation: CTTMar, UNIVALI, Itajai, Brazil (Zeferino, C.A.)
Abstract	Networks-on-Chip (NoCs) emerge as the solution for the problem of interconnecting cores (or IPs) in systems-on-chip (SoCs) which require reusable and scalable communication architectures. The building block of a NoC is its router (or switch), whose architecture has great impact on the costs and on the performance of the network. This work presents a parameterizable router architecture for NoCs which is based on a canonical template and on a library of building components offering different alternatives and implementations for the circuits used for packet forwarding in a NoC. Such features allow to explore the NoC design space in order to obtain a router configuration which best fits the performance requirements of a target application at lower silicon costs. We describe the router architecture and present some synthesis results which demonstrate the feasibility of this new router.
Sponsorship	Brazilian Comput. Soc. Brazilian Microelectronics Soc. ACM SIGDA IEEE CAS
Starting Page	204
Ending Page	209
File Size	481327
Page Count	6
File Format	PDF
ISBN	1581139470
DOI	10.1109/SBCCI.2004.240876
Language	English
Publisher	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Publisher Date	2004-09-11
Publisher Place	Brazil
Access Restriction	Subscribed
Rights Holder	Association for Computing Machinery, Inc. (ACM)
Subject Keyword	Switches Network-on-a-chip Integrated circuit interconnections Costs Libraries Silicon Permission Design methodology Communication switching Buildings
Content Type	Text
Resource Type	Article

Sl.	Authority	Responsibilities	Communication Details
1	Ministry of Education (GoI), Department of Higher Education	Sanctioning Authority	https://www.education.gov.in/ict-initiatives
2	Indian Institute of Technology Kharagpur	Host Institute of the Project: The host institute of the project is responsible for providing infrastructure support and hosting the project	https://www.iitkgp.ac.in
3	National Digital Library of India Office, Indian Institute of Technology Kharagpur	The administrative and infrastructural headquarters of the project	Dr. B. Sutradhar bsutra@ndl.gov.in
4	Project PI / Joint PI	Principal Investigator and Joint Principal Investigators of the project	Dr. B. Sutradhar bsutra@ndl.gov.in Prof. Saswat Chakrabarti will be added soon
5	Website/Portal (Helpdesk)	Queries regarding NDLI and its services	support@ndl.gov.in
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8	Digital Preservation Centre (DPC)	Assistance with digitizing and archiving copyright-free printed books	dpc@ndl.gov.in
9	IDR Setup or Support	Queries related to establishment and support of Institutional Digital Repository (IDR) and IDR workshops	idr@ndl.gov.in

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