NDLI: A 1.8 V supply multi-frequency digitally trimmable on-chip IC oscillator with low-voltage detection capability

Content Provider	IEEE Xplore Digital Library
Author	Boas, A.L.V. Soldera, J.B.D. Olmos, A.
Copyright Year	2004
Description	Author affiliation: Motorola - Brazil Semicond. Technol. Center, Sao Paulo, Brazil (Boas, A.L.V.; Soldera, J.B.D.; Olmos, A.)
Abstract	The design of a 1.8V power supply, multi-frequency on-chip IC oscillator with a built-in low voltage detection (LVD) circuitry is described. Since the modules share the same bandgap cell, the system includes a new bandgap isolation strategy based on wide swing cascode current mirrors to reduce noise coupling into the LVD. The IC oscillator generates four selectable clock frequencies: 4 MHz and 8 MHz from 1.8 V to 5.5 V, 12 MHz and 22 MHz from 2.7 V to 5.5 V. After fine-tuning the oscillator via digital trimming its output frequency varies less than /spl plusmn/2.5% around the target frequency over supply ranges and from -40 to 125/spl deg/C. The measured clock jitter is below 0.1% whereas the recover time from stop is 5 /spl mu/s. The low voltage detection circuit monitors the supply voltage applied to the system and generates the appropriate warning or even initiates a system shutdown before the in-circuit SoC presents malfunction. The module was implemented in a 0.5 /spl mu/m CMOS technology, occupies an area of 360/spl times/530 /spl mu/m/sup 2/ and requires no external reference or components.
Sponsorship	Brazilian Comput. Soc. Brazilian Microelectronics Soc. ACM SIGDA IEEE CAS
Starting Page	44
Ending Page	48
File Size	333040
Page Count	5
File Format	PDF
ISBN	1581139470
DOI	10.1109/SBCCI.2004.240975
Language	English
Publisher	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Publisher Date	2004-09-11
Publisher Place	Brazil
Access Restriction	Subscribed
Rights Holder	Association for Computing Machinery, Inc. (ACM)
Subject Keyword	Digital integrated circuits Oscillators Frequency Low voltage Photonic band gap Clocks CMOS technology Power supplies Mirrors Noise reduction
Content Type	Text
Resource Type	Article

Sl.	Authority	Responsibilities	Communication Details
1	Ministry of Education (GoI), Department of Higher Education	Sanctioning Authority	https://www.education.gov.in/ict-initiatives
2	Indian Institute of Technology Kharagpur	Host Institute of the Project: The host institute of the project is responsible for providing infrastructure support and hosting the project	https://www.iitkgp.ac.in
3	National Digital Library of India Office, Indian Institute of Technology Kharagpur	The administrative and infrastructural headquarters of the project	Dr. B. Sutradhar bsutra@ndl.gov.in
4	Project PI / Joint PI	Principal Investigator and Joint Principal Investigators of the project	Dr. B. Sutradhar bsutra@ndl.gov.in Prof. Saswat Chakrabarti will be added soon
5	Website/Portal (Helpdesk)	Queries regarding NDLI and its services	support@ndl.gov.in
6	Contents and Copyright Issues	Queries related to content curation and copyright issues	content@ndl.gov.in
7	National Digital Library of India Club (NDLI Club)	Queries related to NDLI Club formation, support, user awareness program, seminar/symposium, collaboration, social media, promotion, and outreach	clubsupport@ndl.gov.in
8	Digital Preservation Centre (DPC)	Assistance with digitizing and archiving copyright-free printed books	dpc@ndl.gov.in
9	IDR Setup or Support	Queries related to establishment and support of Institutional Digital Repository (IDR) and IDR workshops	idr@ndl.gov.in

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