NDLI: Will the ASIC survive?

Content Provider	IEEE Xplore Digital Library
Author	Camposano, R.
Copyright Year	2004
Description	Author affiliation: Synopsys Inc., Mountain View, CA, USA (Camposano, R.)
Abstract	ASIC design starts have declined lately and many voices speak of fundamental changes as a result of increasing design costs, predicting even the extinction of ASIC design altogether. ASICs and ASSPs have been a formidable economic force, accounting for over one third of the semiconductor market. Standard cell based designs have also been the major consumer of EDA tools and design technology. However, raising NRE costs which stand at approximately $10 M to design an ASIC at the 130 nm technology node, cost of re-spins, lack of flexibility (compared to programmable solutions) and increasing time to market have prompted the search for other design styles. These include structured ASICs, FPGAs, processor arrays and "platforms", which are all trying to fill the void left by the slowing of ASIC design starts. The reality however is that none has so far proven to be a solution with a wide spectrum of applications, because they are either a limited economic choice or because their performance constraints the application space. This presentation addresses the trade-offs among these design solutions and also looks at several ways of mixing these technologies. These alternative solutions are reviving cell-based design by adding the flexibility of those alternative solutions to the traditional ASIC design.
Sponsorship	Brazilian Comput. Soc. Brazilian Microelectronics Soc. ACM SIGDA IEEE CAS
File Size	35580
File Format	PDF
ISBN	1581139470
DOI	10.1109/SBCCI.2004.240870
Language	English
Publisher	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Publisher Date	2004-09-11
Publisher Place	Brazil
Access Restriction	Subscribed
Rights Holder	Association for Computing Machinery, Inc. (ACM)
Subject Keyword	Application specific integrated circuits Costs Economic forecasting Space technology Electronic design automation and methodology Time to market Field programmable gate arrays
Content Type	Text
Resource Type	Article

Sl.	Authority	Responsibilities	Communication Details
1	Ministry of Education (GoI), Department of Higher Education	Sanctioning Authority	https://www.education.gov.in/ict-initiatives
2	Indian Institute of Technology Kharagpur	Host Institute of the Project: The host institute of the project is responsible for providing infrastructure support and hosting the project	https://www.iitkgp.ac.in
3	National Digital Library of India Office, Indian Institute of Technology Kharagpur	The administrative and infrastructural headquarters of the project	Dr. B. Sutradhar bsutra@ndl.gov.in
4	Project PI / Joint PI	Principal Investigator and Joint Principal Investigators of the project	Dr. B. Sutradhar bsutra@ndl.gov.in Prof. Saswat Chakrabarti will be added soon
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