NDLI: APU: specification and design of a multi algorithm ATM policing unit IP

Content Provider	IEEE Xplore Digital Library
Author	de Lima, J.A.G. Cavalcanti, A.C. Ferreira de Lucena, S.
Copyright Year	2002
Abstract	Today's needs of miniaturization, performance and power consumption of entire "connected" wireless information processing units and time-to-market constraints, impose design strategies that (re)use building IP (intellectual property) blocks with increasing flexibility capabilities. Previous works on ATM layer controllers provided designs of chips/cores of multi/single port single ASIC chips and single FPGA chips that implement several algorithm types, for the entire ATM layer processing, by microinstruction programming only. In order to provide designers with less complex (more reusable) IP for their appliance, this paper presents APU: an IP of a hardware core, designed to execute multi algorithm ATM policing functions only.
Sponsorship	SBC - Brazilian Comput. Soc. SBMicro - Brazilian Microelectron. Soc. IFIP WG10.5 ACM Sigda
Starting Page	35
Ending Page	39
File Size	1275276
Page Count	5
File Format	PDF
ISBN	0769518079
DOI	10.1109/SBCCI.2002.1137634
Language	English
Publisher	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Publisher Date	2002-09-14
Publisher Place	Brazil
Access Restriction	Subscribed
Rights Holder	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Subject Keyword	Algorithm design and analysis Energy consumption Information processing Time to market Buildings Intellectual property Application specific integrated circuits Field programmable gate arrays Home appliances Hardware
Content Type	Text
Resource Type	Article

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1	Ministry of Education (GoI), Department of Higher Education	Sanctioning Authority	https://www.education.gov.in/ict-initiatives
2	Indian Institute of Technology Kharagpur	Host Institute of the Project: The host institute of the project is responsible for providing infrastructure support and hosting the project	https://www.iitkgp.ac.in
3	National Digital Library of India Office, Indian Institute of Technology Kharagpur	The administrative and infrastructural headquarters of the project	Dr. B. Sutradhar bsutra@ndl.gov.in
4	Project PI / Joint PI	Principal Investigator and Joint Principal Investigators of the project	Dr. B. Sutradhar bsutra@ndl.gov.in Prof. Saswat Chakrabarti will be added soon
5	Website/Portal (Helpdesk)	Queries regarding NDLI and its services	support@ndl.gov.in
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9	IDR Setup or Support	Queries related to establishment and support of Institutional Digital Repository (IDR) and IDR workshops	idr@ndl.gov.in

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