NDLI: A new architecture for 2's complement Gray encoded array multiplier

Content Provider	IEEE Xplore Digital Library
Author	Costa, E. Bampi, S. Monteiro, J.
Copyright Year	2002
Description	Author affiliation: UCPel, Pelotas, Brazil (Costa, E.)
Abstract	We present a new architecture for signed multiplication. The proposed architecture maintains the pure form of an array multiplier, exhibiting a much lower overhead than the Booth architecture. We propose a hybrid encoding for the architecture, which is a compromise between the minimal input dependency presented by binary encoding and the low switching characteristic of the Gray encoding. We have experimented using the Gray code for each group of m bits, thus potentially further reducing the switching activity both internally and at the inputs. The architecture is extended for radix-2/sup m/ encoding, which leads to a reduction of the number of partial lines, enabling a significant improvement in performance and power consumption. The flexibility of our architecture allows for the easy construction of multipliers for different values of m. The results we present show that the proposed architecture with radix-4 compares favorably in performance and power with the modified Booth multiplier.
Sponsorship	SBC - Brazilian Comput. Soc. SBMicro - Brazilian Microelectron. Soc. IFIP WG10.5 ACM Sigda
Starting Page	14
Ending Page	19
File Size	298667
Page Count	6
File Format	PDF
ISBN	0769518079
DOI	10.1109/SBCCI.2002.1137631
Language	English
Publisher	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Publisher Date	2002-09-14
Publisher Place	Brazil
Access Restriction	Subscribed
Rights Holder	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Subject Keyword	Encoding Energy consumption Delay Reflective binary codes Digital signal processing Arithmetic Minimization Logic circuits Integrated circuit interconnections Very large scale integration
Content Type	Text
Resource Type	Article

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