NDLI: Comparative analysis of sensing schemes for multilevel non-volatile memories

Content Provider	IEEE Xplore Digital Library
Author	Calligaro, C. Manstretta, A. Pierin, A. Torelli, G.
Copyright Year	1997
Description	Author affiliation: Dept. of Electron., Pavia Univ., Italy (Calligaro, C.)
Abstract	Reading multilevel non-volatile memories is a very demanding task. Three sensing techniques (the parallel scheme, the binary-serial scheme and the mixed parallel-serial scheme) are considered here. Their operation principles are described and a comparative evaluation in terms of both access time and circuit complexity is carried out. The parallel approach is the most suitable for 4-level-cell memories (2 bit per cell). The mixed approach seems to be the most attractive for a large number of programmable levels (at least 16 levels per cell). In this case, the sensing area overhead is limited to less than 1% of the memory array while access time penalty is less than 50%.
Starting Page	266
Ending Page	273
File Size	463745
Page Count	8
File Format	PDF
ISBN	0780342763
ISSN	10947116
DOI	10.1109/ICISS.1997.630269
Language	English
Publisher	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Publisher Date	1997-10-08
Publisher Place	USA
Access Restriction	Subscribed
Rights Holder	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Subject Keyword	Nonvolatile memory Silicon Threshold voltage Complexity theory Costs Fabrication Energy consumption Degradation Technological innovation Current supplies
Content Type	Text
Resource Type	Article

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Comparative analysis of sensing schemes for multilevel non-volatile memories