NDLI: A reconfigurable Markov chain simulator for analysis of parallel systems

Content Provider	IEEE Xplore Digital Library
Author	Yamamoto, O. Shibata, K. Kurosawa, H. Amano, H.
Copyright Year	1997
Description	Author affiliation: Dept. of Electr. Eng., Tokyo Denki Univ., Japan (Yamamoto, O.)
Abstract	Markov chain is a convenient tool to analyze parallel systems for architects who are not experts of theoretical analysis. However, it is sometimes difficult to use especially when the model becomes complicated or extremely small probabilities are used in the model. In this paper, we propose a reconfigurable Markov chain simulation system and evaluate on a reconfigurable testbed. In this system, a user describes the target system in a dedicated description language called "Taico". The description is automatically translated into the Verilog-HDL description, of the Markov chain simulator. Then, the simulator is implemented on a reconfigurable testbed called FLEMING, and executed directly. From the evaluation with analysis of example parallel systems, it appears that the simulation speed of proposed system is more than hundreds times faster than software simulation on a high speed workstation.
Starting Page	107
Ending Page	116
File Size	507250
Page Count	10
File Format	PDF
ISBN	0780342763
ISSN	10947116
DOI	10.1109/ICISS.1997.630251
Language	English
Publisher	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Publisher Date	1997-10-08
Publisher Place	USA
Access Restriction	Subscribed
Rights Holder	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Subject Keyword	Analytical models Hardware design languages Field programmable gate arrays Performance analysis Computer simulation Workstations Programmable logic arrays Circuit simulation Logic testing Computational modeling
Content Type	Text
Resource Type	Article

Sl.	Authority	Responsibilities	Communication Details
1	Ministry of Education (GoI), Department of Higher Education	Sanctioning Authority	https://www.education.gov.in/ict-initiatives
2	Indian Institute of Technology Kharagpur	Host Institute of the Project: The host institute of the project is responsible for providing infrastructure support and hosting the project	https://www.iitkgp.ac.in
3	National Digital Library of India Office, Indian Institute of Technology Kharagpur	The administrative and infrastructural headquarters of the project	Dr. B. Sutradhar bsutra@ndl.gov.in
4	Project PI / Joint PI	Principal Investigator and Joint Principal Investigators of the project	Dr. B. Sutradhar bsutra@ndl.gov.in Prof. Saswat Chakrabarti will be added soon
5	Website/Portal (Helpdesk)	Queries regarding NDLI and its services	support@ndl.gov.in
6	Contents and Copyright Issues	Queries related to content curation and copyright issues	content@ndl.gov.in
7	National Digital Library of India Club (NDLI Club)	Queries related to NDLI Club formation, support, user awareness program, seminar/symposium, collaboration, social media, promotion, and outreach	clubsupport@ndl.gov.in
8	Digital Preservation Centre (DPC)	Assistance with digitizing and archiving copyright-free printed books	dpc@ndl.gov.in
9	IDR Setup or Support	Queries related to establishment and support of Institutional Digital Repository (IDR) and IDR workshops	idr@ndl.gov.in

Solving satisfiability problems using logic synthesis and reconfigurable hardware

A reconfigurable logic machine for fast event-driven simulation

Design and Simulation of Runtime Reconfigurable Systems

A reconfigurable stochastic model simulator for analysis of parallel systems

Reconfiguration of one-time programmable FPGAs with faulty logic resources

Hardware simulation with software modeling for enhanced architecture performance analysis

Accelerated cosimulation using reconfigurable computing

Solving satisfiability problems using reconfigurable computing

Modeling Dynamically Reconfigurable Systems for Simulation-Based Functional Verification

A reconfigurable Markov chain simulator for analysis of parallel systems

Similar Documents

Solving satisfiability problems using logic synthesis and reconfigurable hardware

A reconfigurable logic machine for fast event-driven simulation

Design and Simulation of Runtime Reconfigurable Systems

A reconfigurable stochastic model simulator for analysis of parallel systems

Reconfiguration of one-time programmable FPGAs with faulty logic resources

Hardware simulation with software modeling for enhanced architecture performance analysis

Accelerated cosimulation using reconfigurable computing

Solving satisfiability problems using reconfigurable computing

Modeling Dynamically Reconfigurable Systems for Simulation-Based Functional Verification

A reconfigurable Markov chain simulator for analysis of parallel systems