NDLI: Architecture and compiler co-optimization for high performance computing

Content Provider	IEEE Xplore Digital Library
Author	Nakamura, H. Kondo, M. Ohneda, T. Fujita, M. Chiba, S. Sato, M. Boku, T.
Copyright Year	2002
Description	Author affiliation: Res. Center for Adv. Sci. & Technol., Univ. of Tokyo, Japan (Nakamura, H.; Kondo, M.; Ohneda, T.; Fujita, M.)
Abstract	The performance gap between processor and memory is very serious problem in high-performance computing because effective performance is limited by memory ability. In order to overcome this problem, it is indispensable to make good use of wide on-chip memory bandwidth. For this purpose, architecture and compiler co-optimization is a promising approach because most data access is regular and/or predictable in high performance computing. Thus, we propose a new VLSI architecture called SCIMA as a platform of the co-optimization. SCIMA integrates software controllable memory (SCM) into a processor chip in addition to ordinary data cache. SCM and cache can be reconfigured by software during computation. Hence, the memory hierarchy itself is the target of compiler optimization. In this sense, architecture and compiler co-optimization is realized in SCIMA. Towards the co-optimization, we have developed a directive-based compiler and an algorithm of SCM usage to insert directives automatically. In this paper, we present the directives and the outline of the algorithm for automatic optimization.
Starting Page	50
Ending Page	56
File Size	710771
Page Count	7
File Format	PDF
ISBN	0769516351
ISSN	15373223
DOI	10.1109/IWIA.2002.1035018
Language	English
Publisher	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Publisher Date	2002-01-11
Publisher Place	USA
Access Restriction	Subscribed
Rights Holder	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Subject Keyword	Computer architecture High performance computing Bandwidth Delay Hardware Electronic mail Very large scale integration Optimizing compilers Throughput Prefetching
Content Type	Text
Resource Type	Article

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1	Ministry of Education (GoI), Department of Higher Education	Sanctioning Authority	https://www.education.gov.in/ict-initiatives
2	Indian Institute of Technology Kharagpur	Host Institute of the Project: The host institute of the project is responsible for providing infrastructure support and hosting the project	https://www.iitkgp.ac.in
3	National Digital Library of India Office, Indian Institute of Technology Kharagpur	The administrative and infrastructural headquarters of the project	Dr. B. Sutradhar bsutra@ndl.gov.in
4	Project PI / Joint PI	Principal Investigator and Joint Principal Investigators of the project	Dr. B. Sutradhar bsutra@ndl.gov.in Prof. Saswat Chakrabarti will be added soon
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