NDLI: Reducing power with an L0 instruction cache using history-based prediction

Content Provider	IEEE Xplore Digital Library
Author	Weiyu Tang Veidenbaum, A.V. Nicolau, A.
Copyright Year	2002
Description	Author affiliation: Dept. of Inf. & Comput. Sci., California Univ., Irvine, CA, USA (Weiyu Tang; Veidenbaum, A.V.; Nicolau, A.)
Abstract	Advances in semiconductor technology have several impacts on processor design. One impact is that faster clock rates and slower wires will limit the number of transistors reachable in a single cycle. Another impact is that power management is becoming a design constraint due to increase in power density. A small L0 cache on top of a traditional L1 cache has the advantages of shorter access time and lower power consumption. The downside of a L0 cache is possible performance loss in the case of cache misses. In this paper, we have analyzed L0 instruction cache miss patterns and have proposed an effective L0 instruction cache management scheme through history-based prediction. For SPEC2000 benchmarks, the prediction hit rate is as high as 99% and the average hit rate is more than 93%. Compared to other L0 instruction cache management schemes, our scheme reduces more than 95% the performance degradation in L0 caches while maintaining the energy advantage as shown by a lower energy-delay product.
Starting Page	11
Ending Page	18
File Size	1010317
Page Count	8
File Format	PDF
ISBN	0769516351
ISSN	15373223
DOI	10.1109/IWIA.2002.1035013
Language	English
Publisher	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Publisher Date	2002-01-11
Publisher Place	USA
Access Restriction	Subscribed
Rights Holder	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Subject Keyword	Prefetching Energy management Energy consumption Pattern analysis Degradation Delay Pipelines Predictive models Computer science Process design
Content Type	Text
Resource Type	Article

Sl.	Authority	Responsibilities	Communication Details
1	Ministry of Education (GoI), Department of Higher Education	Sanctioning Authority	https://www.education.gov.in/ict-initiatives
2	Indian Institute of Technology Kharagpur	Host Institute of the Project: The host institute of the project is responsible for providing infrastructure support and hosting the project	https://www.iitkgp.ac.in
3	National Digital Library of India Office, Indian Institute of Technology Kharagpur	The administrative and infrastructural headquarters of the project	Dr. B. Sutradhar bsutra@ndl.gov.in
4	Project PI / Joint PI	Principal Investigator and Joint Principal Investigators of the project	Dr. B. Sutradhar bsutra@ndl.gov.in Prof. Saswat Chakrabarti will be added soon
5	Website/Portal (Helpdesk)	Queries regarding NDLI and its services	support@ndl.gov.in
6	Contents and Copyright Issues	Queries related to content curation and copyright issues	content@ndl.gov.in
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