NDLI: Addressing the Challenges of System-On-A-Chip Design

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Proceedings European Design and Test Conference. ED & TC 97

Proceedings ED&TC European Design and Test Conference

Proceedings of European Design and Test Conference

Silicon technology: risks, opportunities, and challenges

Future of testing: Reintegration of design, testing and manufacturing

Addressing the Challenges of System-On-A-Chip Design

K*BMDs: a new data structure for verification

Exploiting functional dependencies in finite state machine verification

An efficient algorithm for real-time symbolic model checking

The use of microelectronics for future telecom and multimedia systems

System design tools for broadband telecom network applications

Design challenges of high speed ATM communication ASICs

Deterministic pattern generation for weighted random pattern testing

Deterministic test pattern reproduction by a counter

Multiplicative window generators of pseudo-random test vectors

High-level synthesis of gracefully degradable ASICs

High-level synthesis of recoverable microarchitectures

Reducing address bus transition for low power memory mapping

Assessing the quality level of digital CMOS ICs under the hypothesis of nonuniform distribution of fault probabilities

Surprises in sequential redundancy identification

Optimal code placement of embedded software for instruction caches

A graph based processor model for retargetable code generation

Operation serializability for embedded systems

I/sub DDQ/: you heard the hype, but what's really coming?

Decentralized BIST for 1149.1 and 1149.5 based interconnects

Test structures on MCM active substrate: is it worthwhile?

Relay propagation scheme for testing of MCMs on large area substrates

A specification invariant technique for regularity improvement between flow-graph clusters

An evolution programming approach on multiple behaviors for the design of application specific programmable processors

Area and timing estimation for lookup table based FPGAs

Detailed-routability of FPGAs with extremal switch-block structures

Timing driven placement reconfiguration for fault tolerance and yield enhancement in FPGAs

A timing-constrained incremental routing algorithm for symmetrical FPGAs

Built-in self test architectures for multistage interconnection networks

Designing self-testable multi-chip modules

Achieving fault secureness in parity prediction arithmetic operators: general conditions and implementations

Asynchronous SRT dividers: the real cost

Error detection in fault secure controllers using state encoding

Power optimization of delay constrained CMOS bus drivers

Gate sizing: a general purpose optimization approach

Optimizing CMOS circuits for low power using transistor reordering

Design and selection of buffers for minimum power-delay product

An algorithm for zero-skew clock tree routing with buffer insertion

A balanced-mesh clock routing technique using circuit partitioning

Constructing minimal spanning/Steiner trees with bounded path length

Automatic test generation for maximal diagnosis of linear analog circuits

FLAMES: A fuzzy logic ATMS and model-based expert system for analog diagnosis

Evaluation of i/sub DD//v/sub OUT/ cross-correlation for mixed current-voltage testing of analogue and mixed-signal circuits

DFSIM: a gate-delay fault simulator for sequential circuits

Model refinement for hardware-software codesign

Design of an optimal loosely coupled heterogeneous multiprocessor system

Thread-based software synthesis for embedded system design

An efficient algorithm for signal flow determination in digital CMOS VLSI

Bounding switching activity in CMOS circuits using constraint resolution

An approach for a dynamic generation/validation system for the functional simulation considering timing constraints

VLSI architecture for motion estimation using the block-matching algorithm

High rate soft output Viterbi decoder

A hardware/software concurrent design for a real-time SP@ML MPEG2 video-encoder chip set

Constructive analysis of cyclic circuits

Sequential permissible functions and their application to circuit optimization

Structural methods for the synthesis of speed-independent circuits

Observable time windows: verifying the results of high-level synthesis

PALACE: A parallel and hierarchical layout analyzer and circuit extractor

Including higher-order moments of RC interconnections in layout-to-circuit extraction

Alternating strategies for sequential circuit ATPG

Advanced techniques for GA-based sequential ATPGs

On test generation for interconnected finite-state machines-the output sequence justification problem

A novel analog module generator environment

XPRESS: a cell layout generator with integrated transistor folding

Perturb and simplify: optimizing circuits with external don't cares

Rapid gate matching with don't cares

An implicit algorithm for support minimization during functional decomposition

Towards a uniform notation for memory tests

Test and testability techniques for open defects in RAM address decoders

RAM testing algorithms for detection multiple linked faults

High level CAD melds microsystems with foundries

A conceptual design environment for micromechanisms

SUZANA: a 3D CAD tool for anisotropically etched silicon microstructures

Recursive bipartitioning of signal flow graphs for programmable video signal processors

An automatic hardware-software partitioner based on the possibilistic programming

Hardware/software partitioning using integer programming

Partial scan high-level synthesis

Resynthesis of combinational circuits for path count reduction and for path delay fault testability

A fast optimal robust path delay fault testable adder

A memory-based architecture for MPEG2 System protocol LSIs

Incorporating multi-chip module packaging constraints into system design

FORM: a frame-oriented representation method for digital telecommunication system design

Defect-oriented experiments in fault modelling and fault simulation of microsystem components

Applied design and analysis of microsystems

Step by step from specification to realization of an electrochemical microsystem

Exploit analog IFA to improve specification based tests [of SC circuits]

Analogue fault modelling and simulation for supply current monitoring

Approaches to on-chip testing of mixed signal macros in ASICs

Fast computation of substrate resistances in large circuits

ETS-A: a new electrothermal simulator for CMOS VLSI circuits

Simulated annealing algorithm with multi-molecule: an approach to analog synthesis

Iddq testing for high performance CMOS-the next ten years

Analysis of ISSQ/IDDQ testing implementation and circuit partitioning in CMOS cell-based design

Design for testability of gated-clock FSMs

VLSI design of a high speed soft decision Viterbi detector

A hardware/software codesign case study: design of a robot arm controller

A technique for avoiding isomorphic netlists in architectural synthesis

Algebraic support for transformational hardware allocation

A spectral method for Boolean function matching

FPGA synthesis for minimum area, delay and power

An efficient method for the self-consistent electro-thermal simulation and its integration into a CAD framework

A system for modelling and proving circuits

Exploiting partitioned transition relations for efficient symbolic model checking in CTL

Formal specification of a reactive system: an exercise in VHDL, LOTOS and UNITY

Generalized Recognition Of Gates: a VLSI abstraction tool

A combined pairing and chaining algorithm for CMOS layout generation

Self-checking and fault tolerant approaches can help BIST fault coverage: a case study

Hardware check of arithmetic devices with abridged execution of operations

Realistic fault extraction for boards

Applying behavioural level test generation to high-level design validation

Design of test modules for the analysis of MCM interconnects

Economics modelling and optimisation of MCM test strategies

System fault diagnosis based on a fuzzy qualitative approach

An automated design environment for micromechanical sensors

Methods and tools for the design of electrostatic micromotors

Design kit for microsystems design for an enhanced CMOS process

Proceedings the European Design and Test Conference. ED&TC 1995

Proceedings of European Design and Test Conference EDAC-ETC-EUROASIC

Addressing the Challenges of System-On-A-Chip Design

Content Provider	IEEE Xplore Digital Library
Author	House, G.
Copyright Year	1996
Abstract	Summary form only given, as follows. While systems-on-silicon (SOS) products can range from cellular phones to 200-pound avionics communications and navigation systems, they present common problems to the EDA and semiconductor industries. First, SOS applications demand very high levels of integration and functionality, which can only be met through new sub-micron IC technologies. Second, they embrace both the digital and analog domains with equal complexity, and demand tools that integrate these domains into a single silicon chip. Third, to deliver the required bandwidths, SOS applications must run at very high clock speeds and often operate in the RF realm, with all its attendant design challenges. The author will show how current EDA methodologies and tool technologies will evolve to fit the system on silicon paradigm. In the course of this evolution, the EDA resources used to implement rapid time-to-market designs-top-down synthesis into FPGA or ASIC formats-will migrate into the realm of more complex, full-custom designs that embrace entire electronic systems. This migratory pattern will not be without its challenges. Top-down design flows for FPGAs and ASICs have matured into highly integrated processes that reconcile the creation, synthesis, and physical layout phases of the design cycle. As these same EDA tools migrate into the custom IC arena of systems on silicon, they must retain the integrity of their processes and flows-even though they are now dealing with unprecedented levels of complexity, and integrating software development tools. Further, they must provide an effective means of preserving and exploiting intellectual property for design re-use. In addition, the author will address such issues as the role of power management, integrated design flow, and deep submicron physical effects that are associated with successfully overcoming the challenges of system-on-silicon design.
File Size	74650
File Format	PDF
ISBN	0818674245
ISSN	10661409
DOI	10.1109/EDTC.1996.494117
Language	English
Publisher	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Publisher Date	1996-03-11
Publisher Place	France
Access Restriction	Subscribed
Rights Holder	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Subject Keyword	System-on-a-chip Silicon Electronic design automation and methodology Application specific integrated circuits Field programmable gate arrays Power system management Graphics Cellular phones Aerospace electronics Navigation
Content Type	Text
Resource Type	Article

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