NDLI: Implementing a quantitative model for the 'effective' signal processing in the auditory system on a dedicated digital VLSI hardware

Content Provider	IEEE Xplore Digital Library
Author	Schwarz, A. Mertsching, B. Brucke, M. Nebel, W. Tschorz, J. Kollmeier, B.
Copyright Year	1999
Description	Author affiliation: Dept. of Comput. Sci., Hamburg Univ., Germany (Schwarz, A.)
Abstract	A digital VLSI implementation of an algorithm modeling the 'effective' signal processing of the human auditory system is presented. The model consists of several stages psychoacoustically and physiologically motivated by the signal processing in the human ear and was successfully applied to various speech processing applications. The processing scheme was partitioned for implementation in a set of three chips. Due to local properties of the signal dynamic and the necessary arithmetical precision different approaches for number representation and appropriate arithmetic operators were investigated and implemented. It is demonstrated how an application of the model has been used to determine the necessary wordlengths for a transfer of the algorithm into a version suitable for hardware implementation. Fix point arithmetic is used in the linear parts of the origin algorithm and a special small floating point operator set was developed for the nonlinear part. This part was coded in behavioral VHDL and synthesized with Synopsys Behavioral Compiler. The hardware algorithm is being evaluated on different implementation levels for a FPGA and will be manufactured as ASICs in a later version. The presented FPGA chip set will be combined with a commercial DSP system (TMS320C6201) for real time and reconfigurable signal processing.
Starting Page	133
Ending Page	139
File Size	85456
Page Count	7
File Format	PDF
ISBN	0769503217
ISSN	10896503
DOI	10.1109/EURMIC.1999.794459
Language	English
Publisher	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Publisher Date	1999-09-08
Publisher Place	Italy
Access Restriction	Subscribed
Rights Holder	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Subject Keyword	Signal processing algorithms Psychoacoustic models Digital signal processing chips Humans Hardware Field programmable gate arrays Very large scale integration Partitioning algorithms Auditory system Psychology
Content Type	Text
Resource Type	Article

Sl.	Authority	Responsibilities	Communication Details
1	Ministry of Education (GoI), Department of Higher Education	Sanctioning Authority	https://www.education.gov.in/ict-initiatives
2	Indian Institute of Technology Kharagpur	Host Institute of the Project: The host institute of the project is responsible for providing infrastructure support and hosting the project	https://www.iitkgp.ac.in
3	National Digital Library of India Office, Indian Institute of Technology Kharagpur	The administrative and infrastructural headquarters of the project	Dr. B. Sutradhar bsutra@ndl.gov.in
4	Project PI / Joint PI	Principal Investigator and Joint Principal Investigators of the project	Dr. B. Sutradhar bsutra@ndl.gov.in Prof. Saswat Chakrabarti will be added soon
5	Website/Portal (Helpdesk)	Queries regarding NDLI and its services	support@ndl.gov.in
6	Contents and Copyright Issues	Queries related to content curation and copyright issues	content@ndl.gov.in
7	National Digital Library of India Club (NDLI Club)	Queries related to NDLI Club formation, support, user awareness program, seminar/symposium, collaboration, social media, promotion, and outreach	clubsupport@ndl.gov.in
8	Digital Preservation Centre (DPC)	Assistance with digitizing and archiving copyright-free printed books	dpc@ndl.gov.in
9	IDR Setup or Support	Queries related to establishment and support of Institutional Digital Repository (IDR) and IDR workshops	idr@ndl.gov.in

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