NDLI: A novel approach for CMOS parallel counter design

Content Provider	IEEE Xplore Digital Library
Author	Rong Lin Kerr, K.E. Botha, A.S.
Copyright Year	1999
Description	Author affiliation: Dept. of Comput. Sci., State Univ. of New York, Geneseo, NY, USA (Rong Lin)
Abstract	This paper presents novel low-power high-performance CMOS parallel counter circuits based on recently proposed shift switch logic utilizing state signals and shift switches. The new circuits include a family of (4,2) and (7,3) parallel counters and an efficient 8 bit ripple-carry adder block. The circuits presented in this paper possess the following features: (1) compared with circuits employing binary logic schemes, a reduction of nearly 40-50% in worst-case power dissipation through the use of 4 bit state signals, where no more than half of the signal bits are subject to value-change at any logic stage; (2) high speed which is competitive with well-known circuits; (3) all critical paths contain only minimum-size buffers (inverters or NAND gates) whose nMOS and pMOS transistors can be minimum-sized with a negligible effect on circuit speeds; and (4) the height of any nMOS pass-transistor tree is no more than three. SPICE simulations have demonstrated the significant reduction in power dissipation and the competitive high speed of this approach, while the preliminary layouts of the circuits have illustrated the small VLSI area and the compactness of the design.
Starting Page	112
Ending Page	119
File Size	93811
Page Count	8
File Format	PDF
ISBN	0769503217
ISSN	10896503
DOI	10.1109/EURMIC.1999.794456
Language	English
Publisher	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Publisher Date	1999-09-08
Publisher Place	Italy
Access Restriction	Subscribed
Rights Holder	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Subject Keyword	Counting circuits CMOS logic circuits Switches Switching circuits Pulse inverters Logic circuits Power dissipation MOS devices Adders MOSFETs
Content Type	Text
Resource Type	Article

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