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| Content Provider | IEEE Xplore Digital Library |
|---|---|
| Author | Ries, W. Just, K.M. |
| Copyright Year | 1991 |
| Description | Author affiliation: Siemens AG, Munich, Germany (Ries, W.; Just, K.M.) |
| Abstract | Shows some aspects of VHDL for synthesis (and simulation) from a very practical view. One of the aspects addressed is the integration of VHDL into current design flows with respect to the need of graphical interfaces. A synthesis example shows the advantage of VHDL to facilitate the specification of the structure of a block's architecture together with its functional description. Comparisons to other means of circuit specification show its expressiveness to cover all practical applications. This gives an estimation of the necessary efforts to port already existing circuit models into VHDL.< |
| Starting Page | 78 |
| Ending Page | 82 |
| File Size | 384014 |
| Page Count | 5 |
| File Format | |
| ISBN | 0818621850 |
| DOI | 10.1109/EUASIC.1991.212889 |
| Language | English |
| Publisher | Institute of Electrical and Electronics Engineers, Inc. (IEEE) |
| Publisher Date | 1991-05-27 |
| Publisher Place | France |
| Access Restriction | Subscribed |
| Rights Holder | Institute of Electrical and Electronics Engineers, Inc. (IEEE) |
| Subject Keyword | Logic Circuit synthesis Digital signal processing Design automation Circuit simulation Hardware design languages Design methodology Signal processing algorithms Flow graphs |
| Content Type | Text |
| Resource Type | Article |
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