NDLI: A data-flow processor for real-time low-level image processing

Content Provider	IEEE Xplore Digital Library
Author	Quenot, G. Zavidovique, B.
Copyright Year	1991
Description	Author affiliation: Lab. Syst. de Perception, DGA/Establissement Tech. Central de l'Armement, Arcueil, France (Quenot, G.; Zavidovique, B.)
Abstract	A chip featuring two coupled data-flow processors (DFPs) has been designed. It is to be mesh-connected into large processor arrays dedicated primarily to image processing. Each processor operates on 25 MBytes/s data-flows and performs up to 50 million 8- or 16-bit arithmetic operations per second. The chip has been processed in a 1 mu m CMOS technology. It includes 160000 transistors in a 84 mm/sup 2/ die size area, its clock is at 25 MHz and it is packaged in a 144-pin PGA package. Computations are performed on the fly on a data-flow that comes from a digital video camera. One physical operator is associated to each operation involved in the algorithm. An experimental data-flow system including eight processors in a 222 3D network has been built. Edge detection, row sums, column sums and histograms have been implemented on it at digital video speed.<>
Starting Page	92
Ending Page	95
File Size	275404
Page Count	4
File Format	PDF
ISBN	0818621850
DOI	10.1109/EUASIC.1991.212887
Language	English
Publisher	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Publisher Date	1991-05-27
Publisher Place	France
Access Restriction	Subscribed
Rights Holder	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Subject Keyword	Image processing Pins CMOS technology Clocks Electronics packaging Digital cameras Image edge detection Histograms Computer architecture Dissolved gas analysis
Content Type	Text
Resource Type	Article

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