NDLI: The Coupler Protection System Upgrade for Lower Hybrid Current Drive on Alcator C-Mod

Content Provider	IEEE Xplore Digital Library
Author	Burke, W. Terry, D.R. Kennedy, H. Stillerman, J. McLean, J. Milne, P.
Copyright Year	2007
Description	Author affiliation: Massachusetts Inst. of Technol., Cambridge (Burke, W.; Terry, D.R.; Kennedy, H.; Stillerman, J.)
Abstract	The MIT Plasma Science and Fusion Center (PSFC) Alcator C-Mod project has implemented a lower hybrid current drive (LHCD) system that uses 12 VKC-7849 Varian (CPI) klystron transmitters to supply up to 3 MW source power at 4.6 GHz. Power from each transmitter is split eight ways using a complex system of waveguides to drive the 96-channel coupler array. The existing Coupler Protection System (CPS) monitors directional coupler forward and reflected power signals at 60 locations in the system and provides 60 channels of voltage standing wave ratio (VSWR) protection for the coupler array. To further improve coupler protection and provide remote adjustability an upgrade to the CPS is underway. The most efficient approach to this upgrade has been to use an existing fast digitizer board design having MDS+ data system communication capabilities and reserve field programmable gate array (FPGA) circuitry. Working closely with the digitizer board manufacturer and designers, D-TACQ Solutions, PSFC engineers are developing CPS fault protection logic for twelve each of the ten channel, 14 bit, 6 MSPS/channel digitizer boards with associated custom rear transition modules (RTM). These boards will provide the protection and data acquisition functions needed to allow programmable, optimized protection and monitoring for the coupler and accessibility to the existing MIT PSFC MDS+ data acquisition and control system. Details of the CPS upgrade system will be presented.
Starting Page	1
Ending Page	4
File Size	1262418
Page Count	4
File Format	PDF
ISBN	9781424411931
DOI	10.1109/FUSION.2007.4337937
Language	English
Publisher	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Publisher Date	2007-06-17
Publisher Place	USA
Access Restriction	Subscribed
Rights Holder	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Subject Keyword	Power system protection Transmitters Coupling circuits Field programmable gate arrays Data acquisition Nuclear and plasma sciences Klystrons Directional couplers Voltage Data systems current drive lower hybrid
Content Type	Text
Resource Type	Article

Sl.	Authority	Responsibilities	Communication Details
1	Ministry of Education (GoI), Department of Higher Education	Sanctioning Authority	https://www.education.gov.in/ict-initiatives
2	Indian Institute of Technology Kharagpur	Host Institute of the Project: The host institute of the project is responsible for providing infrastructure support and hosting the project	https://www.iitkgp.ac.in
3	National Digital Library of India Office, Indian Institute of Technology Kharagpur	The administrative and infrastructural headquarters of the project	Dr. B. Sutradhar bsutra@ndl.gov.in
4	Project PI / Joint PI	Principal Investigator and Joint Principal Investigators of the project	Dr. B. Sutradhar bsutra@ndl.gov.in Prof. Saswat Chakrabarti will be added soon
5	Website/Portal (Helpdesk)	Queries regarding NDLI and its services	support@ndl.gov.in
6	Contents and Copyright Issues	Queries related to content curation and copyright issues	content@ndl.gov.in
7	National Digital Library of India Club (NDLI Club)	Queries related to NDLI Club formation, support, user awareness program, seminar/symposium, collaboration, social media, promotion, and outreach	clubsupport@ndl.gov.in
8	Digital Preservation Centre (DPC)	Assistance with digitizing and archiving copyright-free printed books	dpc@ndl.gov.in
9	IDR Setup or Support	Queries related to establishment and support of Institutional Digital Repository (IDR) and IDR workshops	idr@ndl.gov.in

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