NDLI: Reconfigurable hardware as shared resource for parallel threads

Content Provider	IEEE Xplore Digital Library
Author	Haug, G. Rosenstiel, W.
Copyright Year	1998
Description	Author affiliation: Tubingen Univ., Germany (Haug, G.)
Abstract	Approaches to use FPGAs as reconfigurable coprocessors so far always suffered from two problems. First, the hardware required for communication with the host processor occupied an unacceptable large part of the resources available on the FPGA and second, this communication was so slow that the gained acceleration came to naught. The new Xilinx XC6200 family aims to solve both of these problems. The chips are accessed via an SRAM interface, i.e. the host sees them as part of its memory. Besides the configuration bits, which determine logical behaviour and routing, all internal hip-hops of the XC6200 are accessible for reading as well as for writing. This ensures a high performance, since a 32 bit input or output value can be exchanged between the host and the coprocessor by a single load or store operation. In order to make use of the hardware features of the new Xilinx chip series in workstations and PCs easily, a system is presented which synthesizes hardware out of threads coded in C. The threads are part of the C-program running on the host processor. In this paper this system is referred as the Hardware Thread System (HTS). The run time environment required is called the Universal Coprocessor System (UCS). As hardware platform, a specially designed PCI card is used. Besides the reconfigurable coprocessor XC62xx, it consists of the controller (XC4013e) and buffer/data RAM. The RAM of the card can be mapped into the memory address space of the host; nontheless the controller can transfer data between reconfigurable coprocessor and buffer RAM without disturbing the host.
Starting Page	320
Ending Page	321
File Size	101436
Page Count	2
File Format	PDF
ISBN	0818689005
DOI	10.1109/FPGA.1998.707935
Language	English
Publisher	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Publisher Date	1998-04-17
Publisher Place	USA
Access Restriction	Subscribed
Rights Holder	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Subject Keyword	Hardware Yarn Coprocessors Read-write memory Field programmable gate arrays Random access memory Acceleration Routing Writing Workstations
Content Type	Text
Resource Type	Article

Sl.	Authority	Responsibilities	Communication Details
1	Ministry of Education (GoI), Department of Higher Education	Sanctioning Authority	https://www.education.gov.in/ict-initiatives
2	Indian Institute of Technology Kharagpur	Host Institute of the Project: The host institute of the project is responsible for providing infrastructure support and hosting the project	https://www.iitkgp.ac.in
3	National Digital Library of India Office, Indian Institute of Technology Kharagpur	The administrative and infrastructural headquarters of the project	Dr. B. Sutradhar bsutra@ndl.gov.in
4	Project PI / Joint PI	Principal Investigator and Joint Principal Investigators of the project	Dr. B. Sutradhar bsutra@ndl.gov.in Prof. Saswat Chakrabarti will be added soon
5	Website/Portal (Helpdesk)	Queries regarding NDLI and its services	support@ndl.gov.in
6	Contents and Copyright Issues	Queries related to content curation and copyright issues	content@ndl.gov.in
7	National Digital Library of India Club (NDLI Club)	Queries related to NDLI Club formation, support, user awareness program, seminar/symposium, collaboration, social media, promotion, and outreach	clubsupport@ndl.gov.in
8	Digital Preservation Centre (DPC)	Assistance with digitizing and archiving copyright-free printed books	dpc@ndl.gov.in
9	IDR Setup or Support	Queries related to establishment and support of Institutional Digital Repository (IDR) and IDR workshops	idr@ndl.gov.in

Rapid prototyping of reconfigurable coprocessors

Operating system support for interface virtualisation of reconfigurable coprocessors

Macro-instruction generation for dynamic logic caching

A time-multiplexed FPGA

Reconfigurable processing with field programmable gate arrays

Memory Footprint Reduction for FPGA Routing Algorithms

Run-Time Reconfigurable Array Using Magnetic RAM

A SAT solver using software and reconfigurable hardware

Reconfigurable OPB Coprocessors for a Microblaze Self-Reconfigurable SOC Mapped on Spartan-3 FPGAs

Reconfigurable hardware as shared resource for parallel threads

Similar Documents

Rapid prototyping of reconfigurable coprocessors

Operating system support for interface virtualisation of reconfigurable coprocessors

Macro-instruction generation for dynamic logic caching

A time-multiplexed FPGA

Reconfigurable processing with field programmable gate arrays

Memory Footprint Reduction for FPGA Routing Algorithms

Run-Time Reconfigurable Array Using Magnetic RAM

A SAT solver using software and reconfigurable hardware

Reconfigurable OPB Coprocessors for a Microblaze Self-Reconfigurable SOC Mapped on Spartan-3 FPGAs

Reconfigurable hardware as shared resource for parallel threads