NDLI: Mapping homogeneous computations onto dynamically configurable coarse-grained architectures

Content Provider	IEEE Xplore Digital Library
Author	Dandalis, A. Prasanna, V.K.
Copyright Year	1998
Description	Author affiliation: Dept. of Electr. Eng. Syst., Univ. of Southern California, Los Angeles, CA, USA (Dandalis, A.)
Abstract	FPGAs are fine-grained architectures, mainly designed for implementing bit-level tasks and random logic functions. Their performance is limited for computationally demanding applications over large word length data. A highly promising avenue that is being explored by many research groups is coarse-grained configurable architectures. These architectures are datapath-oriented structures and consist of a small number of powerful, word-based configurable processing elements (PEs). Such architectures can result in greater computational efficiency and high throughput for coarse-grained computing tasks. The key for achieving high performance solutions is efficient mapping of tasks onto above architectures. In addition to achieving high computational rates, partitionability is a desirable characteristic of the mapping. Moreover, the computational efficiency must scale with the size of the architecture. Finally, it must result in a simple PE structure, regular/balanced dataflow and sustainable I/O requirements so that it can be realized in hardware. In this paper we show a methodology for deriving dynamic computation structures for 2 dimensioned homogeneous computations. Homogeneous computations lead to all PEs having the same functionality. The derived dynamic structures match the datapath-oriented nature of coarse-grained architectures and lead to efficient mapping schemes. Our solutions require constant I/O and smaller amount of local memory/PE compared with known solutions.
Starting Page	314
Ending Page	315
File Size	132824
Page Count	2
File Format	PDF
ISBN	0818689005
DOI	10.1109/FPGA.1998.707933
Language	English
Publisher	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Publisher Date	1998-04-17
Publisher Place	USA
Access Restriction	Subscribed
Rights Holder	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Subject Keyword	Computer architecture Design methodology Control systems Processor scheduling Design engineering Field programmable gate arrays Logic functions Computer applications Throughput Hardware
Content Type	Text
Resource Type	Article

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