NDLI: ATB: Area-Time response Balancing algorithm for scheduling real-time hardware tasks

Content Provider	IEEE Xplore Digital Library
Author	Iturbe, X. Benkrid, K. Arslan, T. Martinez, I. Azkarate, M.
Copyright Year	2010
Description	Author affiliation: System Level Integration Group, The University of Edinburgh, EH9 3JL, Scotland, UK (Iturbe, X.; Benkrid, K.; Arslan, T.) \|\| Embedded System-on-Chip Group, IKERLAN-IK4, Mondragón 20500, Basque Country (Spain) (Martinez, I.; Azkarate, M.)
Abstract	This paper describes a novel scheduling algorithm for the execution of hardware tasks with real-time constraints onto partially and dynamically reconfigurable FPGAs. The Area-Time response Balancing scheduling algorithm (ATB) is inspired by the well-known Earliest Deadline First (EDF) algorithm, which is extended with a technique for reducing the fragmentation on FPGA's reconfigurable area. This technique promotes the reuse of the resources that are released when great area tasks finish their execution by smaller area tasks as long as the real-time constraints permit to do so. Providing an exclusively time-based algorithm, such as EDF, with support for dealing with area-related issues ensures the best results. Simulation results reported in this paper show that ATB misses 23% less deadlines than EDF. Moreover, since FPGA's damaged resources provoke unpredictable fragmentation on the device, ATB is currently the best scheduling option to be used in a Reliable Reconfigurable Real-Time Operating System (R3TOS).
Starting Page	224
Ending Page	232
File Size	243661
Page Count	9
File Format	PDF
ISBN	9781424489800
e-ISBN	9781424489831
DOI	10.1109/FPT.2010.5681494
Language	English
Publisher	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Publisher Date	2010-12-08
Publisher Place	China
Access Restriction	Subscribed
Rights Holder	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Subject Keyword	Field programmable gate arrays Hardware Real time systems Resource management Scheduling algorithm Runtime Scheduling
Content Type	Text
Resource Type	Article

Sl.	Authority	Responsibilities	Communication Details
1	Ministry of Education (GoI), Department of Higher Education	Sanctioning Authority	https://www.education.gov.in/ict-initiatives
2	Indian Institute of Technology Kharagpur	Host Institute of the Project: The host institute of the project is responsible for providing infrastructure support and hosting the project	https://www.iitkgp.ac.in
3	National Digital Library of India Office, Indian Institute of Technology Kharagpur	The administrative and infrastructural headquarters of the project	Dr. B. Sutradhar bsutra@ndl.gov.in
4	Project PI / Joint PI	Principal Investigator and Joint Principal Investigators of the project	Dr. B. Sutradhar bsutra@ndl.gov.in Prof. Saswat Chakrabarti will be added soon
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