NDLI: Automatic synthesis of processor arrays with local memories on FPGAs

Content Provider	IEEE Xplore Digital Library
Author	Guiming Wu Yong Dou Miao Wang
Copyright Year	2010
Description	Author affiliation: National Laboratory for Parallel and Distributed Processing, National University of Defense Technology, Changsha, 410073, China (Guiming Wu; Yong Dou) \|\| Jiangnan Institute of Computing Technology, Wuxi, 214083, China (Miao Wang)
Abstract	In this paper, we present an automatic synthesis framework to map loop nests to processor arrays with local memories on FPGAs. An affine transformation approach is firstly proposed to address space-time mapping problem. Then a data-driven architecture model is introduced to enable automatic generation of processor arrays by extracting this data-driven architecture model from transformed loop nests. Some techniques including memory allocation, communication generation and control generation are presented. Synthesizable RTL codes can be easily generated from the architecture model built by these techniques. A preliminary synthesis tool is implemented based on PLUTO, an automatic polyhedral source-to-source transformation and parallelization framework.
Starting Page	249
Ending Page	252
File Size	153562
Page Count	4
File Format	PDF
ISBN	9781424489800
e-ISBN	9781424489831
DOI	10.1109/FPT.2010.5681493
Language	English
Publisher	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Publisher Date	2010-12-08
Publisher Place	China
Access Restriction	Subscribed
Rights Holder	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Subject Keyword	Parallel processing Registers Field programmable gate arrays Radiation detectors Arrays Computational modeling
Content Type	Text
Resource Type	Article

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