NDLI: A concurrent multi-bank memory arbiter for dynamic IP cores using idle skip round robin

Content Provider	IEEE Xplore Digital Library
Author	Kearney, D.A. Veldman, G.
Copyright Year	2003
Description	Author affiliation: Adv. Comput. Res. Centre, South Australia Univ., Mawson Lakes, SA, Australia (Kearney, D.A.; Veldman, G.)
Abstract	We present an implementation of a memory arbiter design that gives dynamic IP cores interfaced to multiple internal networks on the programmable chip concurrent access to multiple banks of the SRAM. The arbiter which uses a new fast version of round robin that we call idle skip, has a small instruction set which is invoked by applications allowing them to read and write multiple memory locations, read and write multiple memory locations in a streaming fashion and perform inter application communication with and without access to external SRAM. An atomic test and set instruction is provided that allows applications on the FPGA to lock regions of memory in arbitrary sized blocks to enable fine grained producer consumer style interaction between the dynamic IP cores and the host, and between dynamic IP cores of the FPGA.
Sponsorship	Xilinx Inc. Celoxica Interdesign Technol. Tokyo Electron Device Ltd. Memec Japan K.K. Elixent Inc. Synplicity Inc. Altera Corp. QuickSilver
Starting Page	411
Ending Page	414
File Size	252457
Page Count	4
File Format	PDF
ISBN	0780383206
DOI	10.1109/FPT.2003.1275789
Language	English
Publisher	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Publisher Date	2003-12-17
Publisher Place	Japan
Access Restriction	Subscribed
Rights Holder	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Subject Keyword	Round robin Random access memory Field programmable gate arrays Read-write memory Computer interfaces Computer networks Concurrent computing Network-on-a-chip Delay Memory management
Content Type	Text
Resource Type	Article

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