NDLI: Modular exponentiation using parallel multipliers

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Proceedings. 2003 IEEE International Conference on Field-Programmable Technology (FPT) (IEEE Cat. No.03EX798)

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2002 IEEE International Conference on Field-Programmable Technology, 2002. (FPT). Proceedings.

Modular exponentiation using parallel multipliers

Content Provider	IEEE Xplore Digital Library
Author	Tang, S.H. Tsui, K.S. Leong, P.H.W.
Copyright Year	2003
Description	Author affiliation: Dept. of Comput. Sci. & Eng;, Chinese Univ. of Hong Kong, Shatin, China (Tang, S.H.; Tsui, K.S.; Leong, P.H.W.)
Abstract	A field programmable gate array (FPGA) semi-systolic implementation of a modular exponentiation unit, suitable for use in implementing the RSA public key cryptosystem is presented. The design is carefully matched with features of the FPGA architecture, utilizing embedded 18/spl times/18-bit multipliers on the FPGA and employing a carry save addition scheme. Using this architecture, a 1024-bit modular exponentiation can operate at 90 MHz on a Xilinx XC2V3000-6 device and perform a 1024-bit RSA decryption in 0.66 ms with the Chinese Remainder Theorem.
Sponsorship	Xilinx Inc. Celoxica Interdesign Technol. Tokyo Electron Device Ltd. Memec Japan K.K. Elixent Inc. Synplicity Inc. Altera Corp. QuickSilver
Starting Page	52
Ending Page	59
File Size	433636
Page Count	8
File Format	PDF
ISBN	0780383206
DOI	10.1109/FPT.2003.1275731
Language	English
Publisher	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Publisher Date	2003-12-17
Publisher Place	Japan
Access Restriction	Subscribed
Rights Holder	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Subject Keyword	Field programmable gate arrays Public key cryptography Hardware Computer architecture Parallel processing Application specific integrated circuits Pipeline processing Clocks Public key Computer science
Content Type	Text
Resource Type	Article

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