NDLI: An FPGA implementation of a special purpose processor for steganography

Content Provider	IEEE Xplore Digital Library
Author	Farouk, H.A. Saeb, M.
Copyright Year	2003
Description	Author affiliation: Comput. Dept., Arab Acad. for Sci., Technol. & Maritime Transp., Alexandria, Egypt (Farouk, H.A.; Saeb, M.)
Abstract	In the well-known "prisoners' problem", a representative example of steganography, two persons attempt to communicate covertly without alerting the warden. One approach to achieve this task is to embed the message in an innocent-looking cover-media. In our model, the message contents are scattered in the cover in a certain way that is based on a secret key known only to the sender and receiver. Therefore, even if the warden discovers the existence of the message, he will not be able to recover it. In other words a covert or subliminal communication channel is opened between two persons who possess a secret key to reassemble its contents. In this article, we propose a video or audio steganographic model in which the hidden message an be composed and inserted in the cover in real-time. This is realized by designing and implementing a secret key steganographic micro-architecture employing Field Programmable Gate Arrays FPGA.
Sponsorship	Xilinx Inc. Celoxica Interdesign Technol. Tokyo Electron Device Ltd. Memec Japan K.K. Elixent Inc. Synplicity Inc. Altera Corp. QuickSilver
Starting Page	395
Ending Page	398
File Size	322610
Page Count	4
File Format	PDF
ISBN	0780383206
DOI	10.1109/FPT.2003.1275785
Language	English
Publisher	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Publisher Date	2003-12-17
Publisher Place	Japan
Access Restriction	Subscribed
Rights Holder	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Subject Keyword	Field programmable gate arrays Steganography SDRAM Communication channels Watermarking Fingerprint recognition Hardware Streaming media Real time systems Performance analysis
Content Type	Text
Resource Type	Article

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1	Ministry of Education (GoI), Department of Higher Education	Sanctioning Authority	https://www.education.gov.in/ict-initiatives
2	Indian Institute of Technology Kharagpur	Host Institute of the Project: The host institute of the project is responsible for providing infrastructure support and hosting the project	https://www.iitkgp.ac.in
3	National Digital Library of India Office, Indian Institute of Technology Kharagpur	The administrative and infrastructural headquarters of the project	Dr. B. Sutradhar bsutra@ndl.gov.in
4	Project PI / Joint PI	Principal Investigator and Joint Principal Investigators of the project	Dr. B. Sutradhar bsutra@ndl.gov.in Prof. Saswat Chakrabarti will be added soon
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