NDLI: Scalable high-throughput SRAM-based architecture for IP-lookup using FPGA

Content Provider	IEEE Xplore Digital Library
Author	Hoang Le Weirong Jiang Prasanna, V.K.
Copyright Year	2008
Description	Author affiliation: Ming Hsieh Dept. of Electr. Eng., Univ. of Southern California, Los Angeles, CA (Hoang Le; Weirong Jiang; Prasanna, V.K.)
Abstract	Most high-speed Internet Protocol (IP) lookup implementations use tree traversal and pipelining. However, this approach results in inefficient memory utilization. Due to available on-chip memory and pin limitations of FPGAs, state-of-the-art designs on FPGAs cannot support large routing tables arising in backbone routers. Therefore, ternary content addressable memory (TCAM) is widely used. We propose a novel SRAM-based linear pipeline architecture, named DuPI. Using a single Virtex-4, DuPI can support a routing table of up to 228 K prefixes, which is 3times the state-of-the-art. Our architecture can also be easily partitioned, so as to use external SRAM to handle even larger routing tables (up to 2 M prefixes), while maintaining a 324 MLPS throughput. The use of SRAM (instead of TCAM) leads to orders of magnitude of reduction in power dissipation. Employing caching to exploit Internet traffic locality, we can achieve a throughput of 1.3 GLPS (billion lookups per second). Our design also maintains packet input order, and supports in-place non-blocking route updates.
Starting Page	137
Ending Page	142
File Size	151548
Page Count	6
File Format	PDF
ISBN	9781424419609
DOI	10.1109/FPL.2008.4629921
Language	English
Publisher	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Publisher Date	2008-09-08
Publisher Place	Germany
Access Restriction	Subscribed
Rights Holder	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Subject Keyword	IP networks Random access memory Routing Pipelines Field programmable gate arrays Throughput Pipeline processing
Content Type	Text
Resource Type	Article

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